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US 5,689,198 AGranted
Circuitry and method for gating information
AssigneeInternational Business Machines Corporation
InventorsLawrence Joseph Merkel, John Stephen Muhich
Life of this patent
Estimating the term…
Abstract
A first inverter includes a first input coupled to a first input node. Also, the first inverter includes a first output coupled to an output node. Further, the first inverter includes a voltage node. A second inverter includes a second input coupled to a second input node. Moreover, the second inverter includes a second output coupled to the voltage node.
Claims5
Circuitry, comprising:
- first and second input nodes;
- an output node;
- a voltage supply node having a first logic state;
- a voltage reference node having a second logic state;
- a first inverter including:
- a first input connected to said first input node;
- a first output connected to said output node;
- a first supply node connected to said voltage supply node;
- and
- a first reference node;
- a second inverter including:
- a second input connected to said second input node;
- a second output connected to said first reference node;
- a second supply node connected to said voltage supply node;
- and
- a second reference node connected to said voltage reference node;
- and
- a p channel field effect transistor ("FET") transistor including:
- a gate coupled to said second input node;
- a source coupled to said voltage supply node;
- and
- a drain coupled to said output node.
19 more elements
A method, comprising:
- sizing first, second, third and fourth transistors of circuitry so that a logic state of an output node is operable to transition:
- within a first period of time after transitioning of a logic state of a first input node;
- and
- within a second period of time after transitioning of a logic state of a second input node, said first period of time being significantly less than said second period of time, said circuitry including a supply node and a reference node, said supply node having a first logic state, said reference node having a second logic state, said first input node being connected to gates of said first and second transistors, said output node being connected to drains of said first and second transistors, said second input node being connected gates of said third and fourth transistors, said reference node being connected to a source of said fourth transistor, said supply node being connected to sources of said first and third transistors, and a source of said second transistor being connected to drains of said third and fourth transistors.
1 more element
Dependencies are inferred from the claim text.