US 5,689,195 AGranted

Programmable logic array integrated circuit devices

AssigneeAltera Corporation

InventorsRichard G. Cliff, Srinivas T. Reddy, Rina Raman, L. Todd Cope, Joseph Huang, Bruce B. Pedersen

Life of this patent

Estimating the term…

Loading patent…

Abstract

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Claims19

Dependent claims

A programmable logic array integrated circuit device comprising:

a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns, each of said regions having a plurality of input terminals and an output terminal and being programmable to perform any of a plurality of logic functions on signals applied to its input terminals in order to produce an output signal applied to its output terminal;
a plurality of interconnection conductors associated with each of said rows and including a first subplurality of full-length conductors which extend continuously adjacent to and along the entire length of the associated row, a second subplurality of half-length conductors which extend continuously adjacent to and along approximately a first half of the length of the associated row, and a third subplurality of half-length conductors which are separate from the half-length conductors in said second plurality and which extend continuously adjacent to and along approximately a second half of the length of the associated row, said first and second halves being substantially mutually exclusive;
a plurality of input connectors associated with each of said regions for programmably selectively connecting each input terminal of said region to any one of a multiplicity of said conductors associated with said region, said multiplicity including at least some of the full-length and some of the half-length conductors adjacent to said region;
and
a plurality of output connectors associated with each of said regions for programmably selectively connecting the output terminal of said region to any of a further multiplicity of said conductors associated with said region, said further multiplicity including at least one of the full-length and one of the half-length conductors adjacent to said region to permit the output of any region in a particular row to be applied to an input of substantially any region in said particular row via said interconnection conductors associated with said particular row.

2 more elements

A programmable logic array integrated circuit device comprising:

a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns, said columns being grouped in mutually exclusive pairs of adjacent columns, each of said regions having a plurality of input terminals and an output terminal and being programmable to perform any of a plurality of logic functions on signals applied to its input terminals in order to produce an output signal applied to its output terminal;
a plurality of interconnection conductors associated with each of said rows and extending adjacent to and along the associated row;
a further plurality of interconnection conductors associated with each of said columns and extending continuously adjacent to and along the associated column;
a plurality of input connectors associated with each of said regions for programmably selectively connecting each input terminal of said region to any of a multiplicity of the conductors adjacent to said region;
a plurality of output connectors associated with each of said regions for programmably selectively connecting a signal applied to said output connectors to at least one of the conductors that are associated with the row that includes said region and to at least one of the conductors that are associated with the column that includes said region;
and
a programmable switch associated with each of said regions for programmably selectively applying to said output connectors that are associated with said region the output signal of said region or the output signal of another region which is adjacent to said region but in the column that is in the pair with the column that includes said region.

4 more elements

A programmable logic array integrated circuit device comprising:

a plurality of regions of programmable logic disposed on said device in a two-dimensional array of intersecting rows and columns, each of said regions being programmable to produce at least one primary output signal which is any of a plurality of logic functions of a plurality of input signals applied to said region, said input signals including a plurality of primary input signals and a secondary input signal, and each of said regions being additionally programmable to produce a secondary output signal which is a logic function of said input signals applied to said region;
a plurality of row conductors associated with each of said rows, the row conductors associated with each row being adjacent to and extending along that row for conveying said primary input or primary output signals for regions in that row;
a plurality of column conductors associated with each of said columns, the column conductors associated with each column being adjacent to and extending along that column for conveying said primary input or primary output signals for regions in that column;
a secondary conductor associated with each region in each row for conveying the secondary output signal of the associated region to provide the secondary input signal of another region in that row, said another region being associated with but spaced from said region along said row by an intervening region which is between said region and said another region.

1 more element

Dependencies are inferred from the claim text.