Method for forming studs and interconnects in a multi-layered semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorNaohiro Shoda
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Abstract
A method of manufacturing a semiconductor device having a stud and interconnect in a dual damascene structure uses selective deposition. The method includes forming a trench including a first opening portion and a second opening portion in a dielectric layer, forming a first adhesion layer on a surface exposed by the first opening portion, forming a second adhesion layer on a surface exposed by the second opening portion, and selectively depositing a conductive material on the first adhesion layer and the second adhesion layer, wherein growth of the conductive material on the second adhesion layer starts after growth of the conductive material on the first adhesion layer has started. The first and second adhesion layers are of different materials.
Claims14
An interconnection structure for a semiconductor device comprising:
- a substrate;
- a dielectric layer formed on said substrate;
- a first opening portion formed in said dielectric layer exposing a first surface on a first level;
- a second opening portion formed in said dielectric layer exposing a second surface on a second level different from the first level, said second opening portion communicating with said first opening portion;
- a first layer of a first material formed on said first surface;
- a second layer of a second material formed on said second surface, said second material being different from said first material;
- and
- a conductive layer formed on said first layer and said second layer, said conductive layer filling said first and second opening portions and said conductive layer being in direct contact with said first layer on said first surface and with said second layer on said second surface.
An interconnection structure for a semiconductor device comprising:
- a substrate;
- a dielectric layer formed on said substrate;
- a first opening portion formed in said dielectric layer exposing a surface of said substrate;
- a second opening portion formed in said dielectric layer, exposing a surface of said dielectric layer, said second opening portion communicating with said first opening portion;
- a first layer of a first material formed on said surface of said substrate;
- a second layer of a second material formed on said surface of said dielectric layer, said second material being different from said first material;
- and
- a conductive layer formed on said first layer and said second layer said conductive layer filling said first and second opening portions and said conductive layer being in direct contact with said first layer on said first surface and with said second layer on said second surface.
An interconnection structure for a semiconductor device comprising:
- a substrate;
- a gate electrode insulated from said substrate;
- source and drain regions formed in said substrate;
- first layers of a first material formed on said gate electrode and said source and drain regions;
- a dielectric layer formed on said gate electrode and said source and drain regions;
- first opening portions formed in said dielectric layer exposing said first layers;
- a second opening portion formed in said dielectric layer exposing a surface of said dielectric layer, said second opening portion communicating with said first opening portions;
- a second layer of a second material formed on said surface of said dielectric layer, said
- second material being different from said first material;
- and a conductive layer formed on said first layers and said second layer, said conductive layer filling said first opening portions and said second opening portion and said conductive layer being in direct contact with said first layers on said first surface and with said second layer on said second surface.
An interconnection structure for a semiconductor device comprising:
- a substrate;
- a dielectric layer formed on said substrate;
- a first opening portion formed in said dielectric layer exposing a surface of said substrate;
- a second opening portion formed in said dielectric layer, exposing a surface of said dielectric layer, said second opening portion communicating with said first opening portion;
- a first layer of a first material formed on said surface of said substrate;
- a second layer of a second material formed on said surface of said dielectric layer, said second material being different from said first material;
- and
- a conductive layer formed on said first layer and said second layer said conductive layer filling said first and second opening portions,
- wherein said first layer is formed substantially evenly across a bottom surface of said first opening portion on said surface of said substrate, a side wall of said first opening portion including two sections, a bottom section contacting said first layer on the bottom surface of said first opening portion and a top section not having said first layer formed thereon.
An interconnection structure for a semiconductor device comprising:
- a substrate;
- a dielectric layer formed on said substrate;
- a first opening portion formed in said dielectric layer exposing a first surface on a first level;
- a second opening portion formed in said dielectric layer exposing a second surface on a second level different from the first level, said second opening portion communicating with said first opening portion;
- a first layer of a first material formed on said first surface;
- a second layer of a second material formed on said second surface and not in contact with said first layer, said second material being different from said first material;
- and
- a conductive layer formed on said first layer and said second layer, said conductive layer filling said first and second opening portions.
Dependencies are inferred from the claim text.