Vertical double-gate field effect transistor
AssigneeInternational Business Machines Corporation
InventorsJack Oon Chu, Louis Lu-Chen Hsu, Jack Allan Mandelman, Yuan-Chen Sun, Yuan Taur
Life of this patent
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Abstract
A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.
Claims9
A vertical double-gate field effect transistor comprising:
- a substrate;
- a source layer disposed on the substrate, the source layer having a first peripheral edge;
- a channel layer disposed on the source layer, the channel layer having a thickness approximately defining a channel length of the transistor, the channel layer further having a second peripheral edge;
- a drain layer disposed on the channel layer, the drain layer having a third peripheral edge;
- a top dielectric layer disposed on the drain layer, having a fourth peripheral edge substantially coincident the first, second and third peripheral edges;
- a vertical gate dielectric layer surrounding a portion of the source, channel and drain layers and in contact with the portion of the source, channel and drain layers at the respective first, second and third peripheral edges;
- and
- a conductive gate surrounding and in contact with the vertical gate dielectric layer and the top dielectric layer.
Dependencies are inferred from the claim text.