CMOS integrated circuit with reduced susceptibility to PMOS punchthrough

A method for fabricating a CMOS integrated circuit, comprising the steps of:

• a.) providing a semiconductor body with monocrystalline semiconductor well regions near the surface thereof, first ones of said well regions being predominantly doped P-type, and second ones of said well regions being predominantly doped N-type, isolation regions being disposed to prevent conduction between ones of said well regions;
• b.) implanting a dosage of acceptor dopants into said second well regions which is sufficient to set the threshold voltage of PMOS transistors to an approximately predetermined value, said implanting being performed with a stopping distance which is selected to provide a predetermined buried channel depth;
• c.) providing a gate dielectric layer over said well regions, and forming a thin film gate electrode in a predetermined pattern over said semiconductor body, some portions of said gate electrode extending over portions of said first well regions to define NMOS channel regions therein, and other portions of said gate electrode extending over portions of said second well regions to define PMOS channel regions therein;
• d.) encapsulating all exposed surfaces of said gate electrode;
• e.) implanting donor dopants into both said first and second well regions, to form N-type lateral field isolation regions near the surface of said second well regions adjacent to said PMOS channel regions therein said implanting step being performed with a stopping depth which will provide a maximum net concentration of N-type dopants at approximately the same depth as said buried channel depth;
• f.) introducing donor dopants into said first well regions only, to form lightly-doped-drain-extension regions near the surface of said first well regions adjacent to said NMOS channel regions therein;
• g.) forming spacer filaments on the sidewalls of said gate electrode;
• h.) forming P-type source/drain regions in portions of said second well regions which are not covered by said gate electrode nor by said spacer filaments, ones of said PMOS channel regions being separated from respectively adjacent ones of said P-type source/drain regions by respective ones of said lateral field isolation regions;
• and
• i.) forming N-type source/drain regions in portions of said first well regions which are not covered by said gate electrode nor by said spacer filaments, ones of said NMOS channel regions being separated from respectively adjacent ones of said N-type source/drain regions by respective ones of said lightly-doped-drain extension regions;
• wherein said step d) is performed before said steps e) and f).