3D stack of IC chips having leads reached by vias through passivation covering access plane
AssigneeIrvine Sensors Corporation
InventorTony K. Johnson
Life of this patent
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Abstract
A process in which a plurality of IC chips are stacked in a unitary structure having a novel method of exposing leads on the access plane of the stack. After a layer of dielectric material has been formed on the access plane, trenches (preferably trenches) are formed, e.g., by wet lithographic processing, which expose the access plane leads. Thereafter terminals are formed on the access plane in contact with the leads. At the wafer level, layers of dielectric material are deposited which are sufficiently thick to permit the subsequent forming of trenches in the access plane dielectric without uncovering any of the silicon of the IC chips.
Claims20
A process of forming a unitary stack of IC chips containing integrated circuitry as part of a dense electronic package having an access plane, comprising these steps;
- forming a plurality of individual IC chips for inclusion in the stack, each having at least one access plane edge;
- forming layers of dielectric material for separating and insulating each chip from adjacent chips in the stack;
- embedding conductive traces in the dielectric material between each pair of adjacent chips, said traces electrically connecting the integrated circuitry to the access plane;
- including adhesive material between a layer of dielectric material and an adjacent chip;
- stacking the chips;
- causing the adhesive material to hold the stack as an integrated structure;
- said structure having an access plane provided by coplanar edges of the stacked chips and coplanar edges of the dielectric chip-separating layers, at which access plane ends of the embedded traces are exposed;
- forming a separate dielectric layer on top of the access plane;
- removing material from certain areas of said separate dielectric layer to form openings which reach down to the access plane ends of the traces;
- and
- depositing metalization on the access plane to provide terminal connections for the traces;
- the conductive traces embedded between each pair of adjacent chips in the stack being spaced from each adjacent chip by a dielectric material sufficiently thick to ensure that the openings which reach down to the access plane ends of the traces do not uncover any portion of any chip surface.
A method for forming a unitary stack of IC chips containing integrated circuitry as part of a dense electronic package having an access plane, comprising these steps;
- providing a wafer having a substantially planar surface and containing numerous IC dice having terminals at the wafer surface;
- forming on the surface of the wafer a first layer of dielectric material;
- forming openings in the first dielectric layer to reach the terminals;
- metalizing to provide separate leads which contact the terminals through the openings and which provide traces supported by the first dielectric layer and extending toward a common edge;
- forming a second layer of dielectric material covering the traces;
- dicing the wafer to provide numerous layers each having an IC chip and dielectric material thereon, and each having traces terminating at the same layer edge;
- stacking the layers in such a way that a stack access plane is created containing parallel layer edges;
- securing the stacked layers together to form a unitary structure in which both the IC chips and the traces extend to the access plane;
- covering the access plane with a layer of dielectric material;
- forming trenches in the access plane dielectric layer, each of which reaches the ends of a plurality of aligned traces in the stack;
- and
- metalizing the access plane to provide terminal connections for the traces, without interconnecting said aligned trace ends reached by a trench.
Dependencies are inferred from the claim text.