US 5,687,388 AGranted

Scalable tree structured high speed input/output subsystem architecture

AssigneeCompaq Computer Corporation

InventorsDavid R. Wooten, Craig A. Miller, Kevin B. Leigh, Robert Brett Costley, Christopher E. Simonich

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Abstract

A point to point connection architecture for a computer I/O subsystem, resulting in a scalable tree structure. A Master I/O Concentrator (MIOC) is connected to the host bus and handles conversion between a bus oriented structure and the tree structure of the I/O subsystem. Ports away from the host bus are downstream ports and conform to a simple byte wide message protocol. Various IOCs and devices can be attached to one of the downstream ports on the MIOC. The MIOC directs transmissions to the appropriate channel based on a geographical addressing scheme. The IOC connections act as further points of branching. Ultimately IOD or I/O devices are reached, having an upstream port for connection to the IOC and a downstream port and internal logic appropriate for the particular peripheral device. Various registers are present in the IOCs and the IODs to allow determination of the topology and particular devices present. Messages and commands are transferred in the I/O subsystem in defined packets. Various read, write and exchange commands are used, with a read response being utilized to allow split transaction read operations. Certain status and control commands are also present. Interrupts are handled by having the interrupt levels correspond to memory addresses of the programmable interrupt controller, thus allowing simple selection of interrupts to be generated by the devices and no need for separate wiring.

Claims27

Dependent claims

A computer system comprising:

a bus having address, data and control portions, said data portion having a first width, wherein data is transferred in a bus operation;
a processor having address, data and control signals, said signals being connected to said bus;
a main memory connected to said bus;
and
an input/output subsystem connected to said bus, said input/output subsystem including:
a plurality of addressable input/output devices receiving and providing packets, each of said input/output devices having an address range unique to that input/output device, each of said packets having a plurality of fields according to a predetermined protocol, said packets including a command portion and being formed of a plurality of elements having a width less than said first width of said data portion of said bus;
and
a master input/output controller connected to said bus and each of said plurality of input/output devices, said master input/output controller operable to transfer data between said bus and each of said plurality of input/output devices, each of said plurality of input/output devices connected to said master input/output controller separately from each other of said plurality of input/output devices, wherein said master input/output controller includes:
a comparator for determining if a bus operation or a plurality of bus operations is directed to one of said plurality of input/output devices by analyzing said address portion of said bus to determine if the address provided on said address portion of said bus corresponds to an address within one of said unique address ranges of said plurality of input/output devices;
a bus operation converter operable to convert said bus operation or said plurality of bus operations to a packet;
a packet transmitter operable to transmit said packet developed from said bus operation converter to said one of said plurality of input/output devices as a series of said plurality of elements forming said packet;
a packet receiver operable to receive a packet from one of said plurality of input/output devices as a series of said plurality of elements forming said packet;
a packet converter operable to convert said packet received from said one of said plurality of input/output devices to a bus operation or a plurality of bus operations;
and
a bus interface operable to provide said bus operation or said plurality of bus operations to said bus.

12 more elements

A computer system comprising:

a bus having address, data and control portions, said data portion having a first width, wherein data is transferred in a bus operation;
a processor having address, data and control signals, said signals being connected to said bus;
a main memory connected to said bus;
and
an input/output subsystem connected to said bus, said input/output subsystem including:
a plurality of addressable input/output devices receiving and providing packets, each of said input/output devices having an address range unique to that input/output device, one of said input/output devices being a hard disk system, each of said packets having a plurality of fields according to a predetermined protocol, said packets including a command portion and being formed of a plurality of elements having a width less than said first width of said data portion of said bus;
and
a master input/output controller connected to said bus and each of said plurality of input/output devices, said master input/output controller operable to transfer data between said bus and each of said plurality of input/output devices, each of said plurality of input/output devices connected to said master input/output controller separately from each other of said plurality of input/output devices, wherein said master input/output controller includes:
a comparator for determining if a bus operation or a plurality of bus operations is directed to one of said plurality of input/output devices by analyzing said address portion of said bus to determine if the address provided on said address portion of said bus corresponds to an address within one of said unique address ranges of said plurality of input/output devices;
a bus operation converter operable to convert said bus operation or said plurality of bus operations to a packet;
a packet transmitter operable to transmit said packet developed from said bus operation converter to said one of said plurality of input/output devices as a series of said plurality of elements forming said packet;
a packet receiver operable to receive a packet from one of said plurality of input/output devices as a series of said plurality of elements forming said packet;
a packet converter operable to convert said packet received from said one of said plurality of input/output devices to a bus operation or a plurality of bus operations;
and
a bus interface operable to provide said bus operation or said plurality of bus operations to said bus.

12 more elements

Dependencies are inferred from the claim text.