Floating point processor supporting hexadecimal and binary modes using common instructions with memory storing a pair of representations for each value

A computer system including two floating point modes supported by a common set of instructions for implementing operations, program use of said instructions thereby being floating point mode independent, said system comprising:

• a storage device including stored information for specifying one of said two floating point modes;
• a floating point processor unit adapted to execute an operation based on any one instruction from among said common set of instructions in accordance with the stored floating point mode, thereby providing for floating point mode independent program use of the instructions;
• a memory adapted to transfer information to and store information from said floating point processor unit, said memory including associated pairs of stored values, each pair including a first stored value and a second stored value, respectively representing a common number represented in a first floating point format and a second floating point format;
• wherein the floating point processor unit executes an instruction for selectively loading an identified storage location with either the first stored value or the second stored value according to the stored floating point mode.