US 5,687,358 AGranted

Accelerator for mounting and interfacing a second CPU onto a motherboard

AssigneeMelco Inc.

InventorsShinsuke Saito, Shigeru Katagiri

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Abstract

The present invention provides an accelerator working in place of a CPU on a motherboard to speed up the processing. The accelerator can realize the high-speed processing even when a clock on the accelerator is not an integral multiple of a clock on the CPU. When a clock frequency of a clock signal CLK on the motherboard is equal to 20 MHz and a maximum frequency of a CPU (3) on an accelerator (100) is equal to 33 MHz, for example, the CPU (3) does not work properly by a doubled clock signal. In such a case, a clock multiplication circuit (3a) multiplies the clock signal CLK by 1.5 times to generate a clock signal CLK15. There are three different patterns in the relationship between the timing of access of the CPU 3 and the timing of access of the motherboard. The accelerator of the invention determines the appropriate timing in each case and allows the access of the CPU 3 to be synchronous with the access of the motherboard.

Claims13

Dependent claims

An accelerator for use in mounting and interfacing a second CPU which functionally replaces a first CPU on a motherboard, said first CPU intended to be driven by a first clock signal having a first period and a first frequency, said accelerator comprising:

mounting means for mounting said second CPU on said motherboard;
clock signal output means for generating a second clock signal from said first clock signal, said clock signal output means being operative to generate a plurality of delayed signals that take the form of a series of consecutively delayed waveform copies of said first clock signal wherein each copy is delayed by a corresponding time period that is less than or equal to one-half of said first period, said clock signal output means being further operative to combine said plurality of delayed signals to generate said second clock signal, wherein the second clock signal has a second frequency that is a non-integral multiple of said first frequency, said clock signal output means also being operative to output said second clock signal to said second CPU;
and
timing signal generating means for generating a timing signal for access of said second CPU in response to an address control signal generated by said second CPU and a synchronous combination of said first clock signal and said second clock signal,
whereby said first clock signal and said second clock signal will automatically synchronize at said synchronous combination without further adjustment.

2 more elements

Dependencies are inferred from the claim text.