Apparatus and method for modeling a graded channel transistor

A transistor model representing a transistor comprising a drain, a source, a gate and a channel region, wherein the channel region comprises a first channel portion and a second channel portion, the first channel portion having a doping concentration greater than a doping concentration of the second channel portion, the model comprising:

• p1 a first transistor model, wherein the first transistor model represents the first channel portion and assumes a first uniform doping concentration of the first channel portion;
• a second transistor model operably coupled to the first transistor model, wherein the second transistor model represents the second channel portion and assumes a second uniform doping concentration of the second channel portion different from the doping concentration of the first channel portion;
• a modeled junction voltage between the first transistor model and the second transistor model, wherein the modeled junction voltage causes the first transistor model and second transistor model to have equal channel currents;
• and
• a composite transistor model, wherein the composite transistor model is derived by combining the first transistor model and the second transistor model to model the physical operation of the transistor.

An integrated circuit comprising a plurality of transistors, wherein at least a portion of the plurality of transistors comprise graded channel transistors each having a drain, a source, a gate, and a channel region, wherein each of the channel regions comprises a first channel portion and a second channel portion, the first channel portion having a doping concentration greater than a doping concentration of the second channel portion, and wherein each of the graded channel transistors is modeled by a model comprising:

• a first transistor model, wherein the first transistor model represents the first channel portion and assumes a first uniform doping concentration;
• a second transistor model operably coupled to the first transistor model, wherein the second transistor model represents the second channel portion and assumes a second uniform doping concentration different from the first uniform doping concentration;
• a modeled junction voltage between the first transistor model and the second transistor model, wherein the modeled junction voltage causes the first transistor model and second transistor model to have equal channel currents;
• and
• a composite transistor model, wherein the composite transistor model is derived by combining the first transistor model and the second transistor model to model the physical operation of the transistor.

A graded channel field effect transistor comprising:

• a source region;
• a first channel portion operably coupled to the source region, wherein the first channel portion has a first doping concentration, and wherein the first channel portion is modeled by a first transistor model, wherein the first transistor model represents the first channel portion and assumes a first uniform doping concentration;
• a second channel portion operably coupled to the first channel portion, wherein the second channel portion has a second doping concentration different than the first doping concentration, wherein the second channel portion is modeled by a second transistor model operably coupled to the first transistor model, wherein the second transistor model represents the second channel portion and assumes a second uniform doping concentration different from the first uniform doping concentration;
• a drain region operably coupled to the second channel portion;
• and
• a gate operably coupled to the first channel portion and the second channel portion, wherein upon the application of a biasing voltage to the gate, the first channel portion and second channel portions invert.

A method for manufacturing a plurality of integrated circuits, wherein the method comprises the steps of:

• (a) receiving an integrated circuit design file, wherein the integrated circuit design file includes the plurality of integrated circuits, and wherein at least a portion of the integrated circuits include graded channel transistors;
• (b) modeling a graded transistor comprising a drain, a source, a gate and a channel region, wherein the channel region comprises a first channel portion and a second channel portion, wherein the first channel portion has a doping concentration greater than a doping concentration of the second channel portion, wherein modeling the graded channel transistor comprises the steps of:
• (i) determining a length and a doping of the first channel portion;
• (ii) determining a length and a doping of the second channel portion;
• (iii) defining a first transistor model for the first channel portion assuming a uniform doping concentration of the first channel portion;
• (iv) defining a second transistor model for the second channel portion assuming a uniform doping concentration of the second channel portion;
• (v) assuming a junction voltage level between the first transistor model and the second transistor model;
• (vi) calculating a channel current of the first transistor model based on the junction voltage;
• (vii) calculating a channel current of the second transistor model based on the junction voltage;
• (viii) repeating steps (v) through (vii) until the channel current of the first transistor model substantially equals the channel current of the second transistor model;
• and
• (ix) combining the first transistor model and the second transistor model to form a composite transistor model for the transistor;
• (c) applying the model to a plurality of graded transistors in the integrated circuit design file to create an integrated circuit design model, wherein the plurality of graded channel transistors are interoperably coupled to operate as one integrated circuit among the plurality of integrated circuits;
• and
• (d) manufacturing the plurality of integrated circuits in accordance with the integrated circuit design model.

A method for determining an intermediate voltage at a junction point in a channel region of a transistor, the transistor comprising a drain, a source, a gate and a channel region, wherein the channel region comprises a first channel portion and a second channel portion, wherein the first channel portion has a doping concentration greater than a doping concentration of the second channel portion, and wherein the junction point lies at an interface between the first channel portion and the second channel portion, the method comprising the steps of:

• (a) determining a first transistor model for the first channel portion assuming a uniform doping concentration of the first channel portion;
• (b) determining a second transistor model for the second channel portion assuming a uniform doping concentration of the second channel portion different than the doping concentration of the first channel portion;
• (c) assuming a junction voltage between the first transistor model and the second transistor model;
• (d) calculating a channel current of the first transistor model based on the junction voltage;
• (e) calculating a channel current of the second transistor model based on the junction voltage;
• and
• (f) repeating steps (a) through (e) until the channel current of the first transistor model substantially equals the channel current of the second transistor model.

A method for creating a model of a transistor, the method comprising the steps of:

• (a) determining a plurality of transistor models, wherein each of the plurality of transistor models represents a portion of a channel of the transistor, wherein each of the plurality of transistor models assumes a uniform doping concentration of a respective channel portion, and wherein at least two of the plurality of transistor models assume differing doping concentrations;
• (b) coupling the plurality of transistor models such that a respective junction voltage level resides between adjacent transistor models;
• (c) assuming a value for each of the respective junction voltage levels;
• (d) calculating a channel current of each of the plurality of transistor models based on the respective junction voltage levels;
• and
• (e) repeating steps (c) through (d) until the channel currents of each of the plurality of transistor models is substantially equal.

A method for modeling a transistor comprising a drain, a source, a gate and a channel region, wherein the channel region comprises a first channel portion, a second channel portion, and a third channel portion, wherein the first channel portion and the third channel portion have a doping concentration greater than a doping concentration of the second channel portion, the method comprising the steps of:

• (a) receiving a geometry and a doping concentration of the first channel portion;
• (b) receiving a geometry and a doping concentration of the second channel portion;
• (c) receiving a geometry and a doping concentration of the third channel portion;
• (d) determining a first transistor model for the first channel portion and the third channel portion assuming a uniform doping concentration of a channel portion of the first transistor model;
• (e) determining a second transistor model for the second channel portion assuming a uniform doping concentration of a channel portion of the second transistor model;
• (f) assuming a junction voltage level between the first transistor model and the second transistor model;
• (g) calculating a channel current of the first transistor model based on the junction voltage;
• (h) calculating a channel current of the second transistor model based on the junction voltage;
• (i) repeating steps (f) through (h) until the channel current of the first transistor model substantially equals the channel current of the second transistor model;
• and
• (j) combining the first transistor model and the second transistor model to form a composite transistor model for the transistor.

A computer readable medium, wherein the computer readable medium comprises:

• (a) instructions for receiving parameters relating to the geometry of a transistor, the transistor comprising a drain, a source, a gate and a channel region, wherein the channel region comprises a first channel portion and a second channel portion, wherein the first channel portion has a doping concentration greater than a doping concentration of the second channel portion, the parameters including a geometry and a doping concentration of the first channel portion and a geometry and a doping concentration of the second channel portion;
• (b) instructions for determining a first transistor model, wherein the first transistor model represents the first channel portion, wherein the first transistor model is based on the geometry and doping of the first channel portion, and wherein the first transistor model assumes a uniform doping concentration;
• (c) instructions for determining a second transistor model, wherein the second transistor model represents the second channel portion, wherein the second transistor model is based on the geometry and doping of the second channel portion, and wherein the second transistor model assumes a uniform doping concentration;
• (d) instructions for assuming a junction voltage level at an interface between the first transistor model and the second transistor model;
• (e) instructions for determining a channel current of the first transistor model based on the junction voltage;
• (f) instructions for determining a channel current of the second transistor model based on the junction voltage;
• (g) instructions for adjusting the junction voltage level until the channel current of the first transistor model substantially equals the channel current of the second transistor model;
• and
• (h) instructions for combining the first transistor model and the second transistor model to form a composite transistor model for the transistor.

A method for modeling a graded complementary metal oxide semiconductor (GCMOS) device having a first channel region portion with a first doping concentration and a second channel region portion with a second doping concentration, the first channel region portion and the second channel region portion defining a total channel length of the GCMOS device, the method comprising the steps of:

• providing a file in memory that contains a plurality of transistors which are collectively interconnected to form an integrated circuit;
• identifying the GCMOS device among the plurality of transistors in memory;
• determining a first parameter for the GCMOS device which is equal to an effective length of the first channel portion;
• determining a second parameter for the GCMOS device which is equal to an fixed doping concentration wherein the fixed doping concentration is a numerically constant approximation of the first doping concentration of the first channel region portion;
• determining at least one third parameter for the GCMOS device which is used to adjust one of either the first or second parameter as a function of the total channel length of the GCMOS device;
• determining at least one fourth parameter for the GCMOS device which is used to model the GCMOS device for reverse operation;
• and
• using the first, second, third, and fourth parameters to verify a correct operation of the integrated circuit.

A method for modeling a graded complementary metal oxide semiconductor (GCMOS) device having a first channel region portion with a first doping concentration and a second channel region portion with a second doping concentration, the first channel region portion and the second channel region portion defining a total channel length of the GCMOS device, the method comprising the steps of:

• providing a file in memory that contains a plurality of transistors which are collectively interconnected to form an integrated circuit;
• identifying the GCMOS device among the plurality of transistors in memory;
• determining a first set of parameters for the GCMOS device which model the GCMOS device when in a forward mode of operation;
• determining a second set of parameters for the GCMOS device which model the GCMOS device when in a reverse mode of operation;
• using the first and second set of parameters to determine if the plurality of transistors are functioning properly;
• and
• altering the file in memory to alter the plurality of transistors in the integrated circuit when a determination is made that the transistors are not functioning properly.

A method for modeling a graded complementary metal oxide semiconductor (GCMOS) device having a first channel region portion with a first doping concentration and a second channel region portion with a second doping concentration, the first channel region portion and the second channel region portion defining a total channel length of the GCMOS device, the method comprising the steps of:

• providing a file in memory that contains a plurality of transistors which are collectively interconnected to form an integrated circuit;
• identifying the GCMOS device among the plurality of transistors in memory, the GCMOS device having a higher maximum transconductance spike as a function of gate voltage when compared to a conventional CMOS device with a substantially uniform channel doping concentration and having a jog in capacitance as a function of gate voltage when compared to a conventional CMOS device with a substantially uniform channel doping concentration;
• determining a set of parameters for the GCMOS device which model the higher maximum transconductance spike as a function of gate voltage and the jog in capacitance as a function of gate voltage inherent in the GCMOS device;
• using the set of parameters to determine if the plurality of transistors are functioning properly within the file in memory;
• and
• altering the file in memory to alter the plurality of transistors in the integrated circuit when a determination is made that the transistors are not functioning properly.