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AssigneeInternational Business Machines Corporation
InventorsTimothy Bucher, Douglas Christopher Hester, John Victor Sell, Cang N. Tran
Estimating the term…
A protocol and system for providing a next read address during an address phase of a write transaction in a data cache unit in a processing unit is disclosed. The processing unit includes the data cache unit and an instruction cache unit both coupled to an address bus and a data bus, respectively. The two buses are further connected to a system memory controller separate from the microprocessor. The protocol and system provide for next read address and a next transaction during the address phase in a current write transaction. The protocol loads a pre-fetched address within a current data transaction and then generates a next line fill address using the pre-fetched address which is concatenated to the current data transaction. The pre-fetched address is used to generate a next line fill address. The line fill address is generated upon determining if a cache read miss has occurred and if so, copying a modified cache line back to the main system memory and then loading the missed cache read line into the internal cache from the system memory controller.
In a processing unit having a cache unit coupled to an address bus and a data bus, which are further connected to a system memory controller outside of said processing unit, a protocol for providing a next read address during the current write transaction, comprising the steps of:
A processing unit having a cache unit coupled to an address bus and a data bus, which are further connected to a system memory controller outside of said processing unit, a system for providing a next read address for the next transaction as provided during the address phase of a current write transaction comprising:
Dependencies are inferred from the claim text.