Data processor with branch target address cache and subroutine return address cache and method of operation
AssigneeMotorola, Inc.
InventorRalph C. McGarity
Life of this patent
Estimating the term…
Abstract
A data processor (10) has a branch and link address cache (.sup.++ BLAC.sup.++) (40) and a Branch Target Address Cache (BTAC) (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine return instructions each time data processor executes a particular subroutine. Upon the second call of the subroutine, control logic (44) stores the half of the data pair identifying the subroutine return instruction and data identifying the return address in the BTAC. The data processor is thereby able to predict the target address of a subroutine return instruction as it is able to predict the target address of traditional branch instructions.
Claims4
A method of operating a data processor comprising the steps of:
- during a first time period, executing a subroutine call instruction in the data processor, the subroutine call instruction comprising an operand, the operand indexing a subroutine;
- executing the subroutine in the data processor;
- executing a subroutine return instruction in the data processor;
- storing a first data pair in a memory array, a first portion of the first data pair indexing the subroutine call instruction, a second portion of the first data pair indexing the subroutine retum instruction;
- during a second time period subsequent to the first time period, fetching the subroutine call instruction in the data processor;
- reading the second portion of the first data pair from the memory array;
- and
- storing a second data pair in a branch target address cache of the data processor, the second data pair comprising the second portion of the first data pair and the operand.
Dependencies are inferred from the claim text.