US 5,687,344 A · Single-chip microcomputer having an expandable address area

Abstract

Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in an 8-bit CPU (1) so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU. This register can be used in its entirety, by dividing it in half or by dividing it in quarters. As a result, the register can be used on software or hardware to reduce the logical and physical scales of the CPU. In respect of the latch of the address data using the register wholly or partially, moreover, the address space to be linearly used can be easily expanded.

Claims17

Dependent claims

A single chip data processing device comprising:

a register which includes a first register portion having a predetermined first bit length and a second register portion having a predetermined second bit length;
an arithmetic and logic operation section coupled to the register and including a first arithmetic and logic unit coupled to the first register portion for executing an arithmetic and logic operation and a second arithmetic and logic unit coupled to the second register portion for executing an arithmetic operation;
and
a condition code register having a plurality of bits whose contents are changed in accordance with an operation of the arithmetic and logic operation section,
wherein the arithmetic and logic operation section executes an address operation between address data stored in the first and the second register portions and first data provided from another location by using the first arithmetic and logic unit and the second arithmetic and logic unit to execute the address operation, and
wherein the arithmetic and logic operation section executes a data operation between second data stored in the first register portion and third data by using the first arithmetic and logic unit to execute the data operation.

3 more elements

A single chip data processing device comprising:

an address register which includes a first register portion having a predetermined first bit length and a second register portion having a predetermined second bit length;
an arithmetic and logic section coupled to the register and including a first arithmetic and logic unit which executes an arithmetic operation and a second arithmetic and logic unit which executes an arithmetic operation, the arithmetic and logic section performing:
an address operation in which the first and second arithmetic and logic units combined to operate on address data from the first and second register portions as a unit and other received data;
a data operation in which the first arithmetic and logic unit operates separately from the second arithmetic and logic unit on data stored in the first register portion and other received data;
and,
a condition code register having a plurality of bits whose contents are changed in accordance with the operation of the arithmetic and logic unit section.

3 more elements

A method of processing data and addresses with a single chip data processing device that includes a register having a first register portion for storing addresses or data of a first bit length and a second register portion for storing addresses or data of a second bit length, the first and second register portions being operable in tandem to store addresses or data of a third bit length equal to the sum of the first and second bit lengths, an arithmetic and logic section having a first arithmetic and logic unit for executing an arithmetic and logic operation and a second arithmetic and logic unit for executing an arithmetic operation, and a condition code register whose contents change in accordance with operations performed by the arithmetic and logic section, the method comprising:

performing an address operation to generate a new address, the address operation including:
retrieving a first address portion from the first register portion and a second address portion from the second register portion,
cooperatively (i) operating on the first address portion and other provided data with the first arithmetic and logic unit and (ii) operating on the second address portion and the other provided data with the second arithmetic and logic unit to cooperatively generate the new address;
performing a data operation, the data operation including:
retrieving data of the first bit length from the first register portion,
performing the arithmetic and logic operation on the first bit length data and other provided data with the first arithmetic and logic unit alone;
updating the conditional code register contents in accordance with the address and data operations.

4 more elements

Dependencies are inferred from the claim text.

Single-chip microcomputer having an expandable address area

Life of this patent

Single-chip microcomputer having an expandable address area

Life of this patent

Abstract

Claims17