Device for speeding up the reading of a memory by a processor

A device for speeding up the reading of a memory by a processor connected to an address bus and a data bus, said processor providing on said address bus, addresses of data in said memory to be sampled off by said processor from said data bus, said device comprising:

• at least two circuits each comprising:
• (i) a memory having addressing inputs and read outputs, (ii) a counter connected to said address bus and to said addressing inputs of said memory, and, (iii) a buffer connected to said data bus and to said read outputs of said memory for receiving a data located in said memory at an address which is applied to said addressing inputs, and (iv) a means for comparing the address supplied by said counter with the address provided by the processor on said address bus, said counter receiving bits of the addresses transmitted by said address bus except at least one lower order bit of said addresses which is stored in a register, said data being stored at same addresses in each of the respective memories of said at least two circuits, and
• a logic circuit for controlling a succession of data transfer cycles at a transmission rate of said transmitted addresses, said logic circuit comprising:
• (i) means for exclusively allowing to transfer at each of said cycles on said data bus as a function of said at least one lower order bit stored in said register data contained in the buffer of one of said at least two circuits only if said comparing means thereof reveals an identity, and for allowing to load said transmitted address in said counters and said register only if said comparing means reveals a discrepancy, and (ii) means for incrementing at each of said cycles the counters of others of said at least two circuits in order to anticipate data transfers of next cycles.