Reduced area floating point processor control logic utilizing a decoder between a control unit and the FPU
AssigneeHewlett-Packard Company
InventorsJon L. Ashburn, Theodore G. Rossin
Life of this patent
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Abstract
A control logic unit outputs a group of encoded control signals that have less redundancy than the FPU signals needed to control a floating point processor, thus requiring fewer signal lines using less area. Decoders electrically connected between the control logic unit and the floating point processor decode the control signals to provide the FPU signals. If the number of control signals is one less than the number of FPU signals, a priority encoder is used as the decoder, unless the FPU signals include a power savings signal. Otherwise a custom decoder is used. The most active signal of the group of FPU signals is selected as the signal to be eliminated when a priority encoder is used.
Claims20
A digital circuit comprising:
- a plurality of control signal outputs, and a control unit providing a control unit signal on each of said signal outputs;
- a floating point unit (FPU), said floating point unit including:
- a plurality of FPU signal inputs, and a plurality of logic units, each said logic units connected to one of said inputs for performing a predetermined function in response to a predetermined FPU signal;
- and
- a decoder electrically connected between said control signal outputs and FPU signal inputs for decoding said control unit signals to provide said FPU signals.
A floating point processor circuit comprising:
- a floating point unit (FPU) including a logic unit for responding to a group of FPU input signals;
- a control unit for producing a group of control unit output signals, said FPU input signals comprising said control unit output signals plus one additional signal;
- and
- a priority encoder electrically connected between said control unit and said floating point unit for producing said group of FPU input signals from said control unit output signals.
A method of reducing the area of the control logic for a logic system including a control unit and a floating point unit (FPU), said floating point unit operating in response to a plurality of FPU signals, said method comprising the steps of:
- analyzing said floating point processor to determine redundant information contained in said FPU signals;
- designing and providing said control unit to provide encoded output signals having less redundancy than said FPU signals;
- and
- providing a decoding unit between said control unit and said floating point unit to decode said encoded signals to provide said FPU signals.
Dependencies are inferred from the claim text.