Pre-reading and pre-decoding of instructions of a microprocessor within single cycle

A method of pre-reading and pre-decoding of instructions of a microprocessor, the method comprising:

• a) pre-reading the next two instructions of a currently executed instruction, said pre-read next two instructions being stored in an odd memory bus and an even memory bus, respectively;
• b) pre-decoding the first one of said pre-read next two instructions, thereby deciding if the pre-decoded first instruction is a jump, call/return, conditional or ordinary instruction;
• and
• c) setting the value of the program counter of the microprocessor to a proper one based on said decision before a next instruction is executed,
• wherein when said pre-decoded first instruction is identified as a conditional instruction, said pre-read instructions stored in either said odd or even memory bus is retrieved and executed based on the operation result of the condition;
• when said pre-decoded first instruction is identified as a jump or call/return instruction, the value of the program counter is set to the address given in said jump or call/return instruction, and at the same time the instructions at next two addresses of said set address are pre-read and respectively stored in said odd and even memory buses, and when said jump or call/return instruction is executed, said jump or call/return instruction is replaced by a NOP (no operation) instruction, such that each of said instructions can be executed within a single clock cycle.