Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

In a processor for speculative execution of instructions, said processor having at least one pipeline and a means for fetching macro instructions, a method of operating said processor comprising the steps of:

• storing a macro instruction in an instruction cache;
• expelling said macro instruction from said instruction cache due to a replacement;
• storing said macro instruction in a victim cache;
• inserting a marker instruction into said pipeline, said marker instruction specifying an entry in said victim cache corresponding to said macro instruction;
• deallocating said entry, and all victim cache entries older than said entry, in said victim cache specified by said marker instruction upon commitment of said marker instruction to an architectural state;
• and, in the event that said victim cache is full and a branch misprediction occurs,
• reinserting said marker instruction into said pipeline.

A computer system comprising:

• a memory device for storing information including macro instructions;
• a bus coupled to said memory device;
• and
• a processor for fetching and speculatively executing instructions, said processor including:
• at least one pipeline;
• an instruction cache coupled to said bus, said instruction cache storing a plurality of macro instructions received from said memory device;
• a victim cache coupled to said instruction cache, said victim cache storing macro instructions expelled from said instruction cache;
• means for inserting a marker instruction in said pipeline when a macro instruction is expelled form said instruction cache, said marker instruction specifying an entry in said victim cache corresponding to said macro instruction, said insertion means reinserting said marker instruction into said pipeline when said victim cache is full and a branch misprediction occurs;
• circuitry for storing an architectural state of said processor;
• and wherein said victim cache further includes state logic that deallocates said entry, and all victim cache entries older than said entry, in said victim cache upon commitment of said marker instruction to said architectural state.