US 5,687,336 A · Stack push/pop tracking and pairing in a pipelined processor

Abstract

A pipelined processor executes several stack instructions simultaneously. Additional shadow registers for stack pointers of instructions in the pipeline are not needed. Instead the new stack pointer is generated once at the end of the pipeline and written to the register file. The stack pointer is needed for generating the stack-top address in memory. The stack-top address is generated early in the pipeline. Other stack instructions in the pipeline which have not yet incremented the stack pointer are located with a stack valid bit array. The stack valid array indicates the increment or decrement amounts for stack instructions in each pipeline stage. An overall displacement or increment value is computed as the sum of all increments and decrements for stack instructions in the pipeline which have not yet updated the stack pointer. The overall displacement which accounts for all unfinished stack instructions is added to the stack pointer from the register file to generate the stack-top address. Thus the new stack pointer does not have to be generated before the stack memory is accessed. Pushes or pops are paired by doubling the increment amount in the stack valid bit array and performing a double-width data transfer.

Claims19

Dependent claims

A pipeline for processing multiple stack instructions comprising:

a plurality of pipeline stages for processing instructions;
a register file for storing operands for input to the pipeline and results from the pipeline;
a stack pointer register for storing a stack pointer indicating a top of a stack;
an array of stack-instruction valid bits for indicating which pipeline stages in the plurality of pipeline stages contain a stack instruction;
stack-top address generating means, receiving stack-instruction valid bits from the array of stack-instruction valid bits, for generating a memory address of the top of the stack in memory;
memory access means, responsive to the memory address from the stack-top address generating means, for transferring data between the stack in memory and the register file;
and
stack pointer update means, receiving the stack pointer, for adding a final adjust to the stack pointer and writing a sum to the stack pointer register when a stack instruction completes processing by the pipeline,
whereby the stack-instruction valid bits indicate which pipeline stages in the plurality of pipeline stages contain a stack instruction, and the stack-instruction valid bits are used to generate the memory address of the stack in memory.

6 more elements

A computer-implemented method for processing multiple stack instructions in a pipeline, the method comprising the steps of:

decoding a stack instruction at the beginning of the pipeline;
reading a stack pointer from a stack-pointer register, the stack pointer not including any increments or decrements for stack instructions in the pipeline which have not completed processing;
determining an overall displacement, the overall displacement being the sum of increments and decrements for stack instructions in the pipeline which have not completed processing;
generating the address of the top of a stack by adding the overall displacement to the stack pointer and to a segment base address, the segment base address being a starting address for a segment containing a stack;
applying the address of the top of the stack to a memory and transferring data between the stack in the memory and a register file for the pipeline;
reading the stack-pointer register and adding the stack pointer to a single-instruction displacement to generate an updated stack pointer, the single-instruction displacement being an increment or decrement for the stack instruction when the stack instruction is about to complete processing by the pipeline;
and
writing the updated stack pointer to the stack-pointer register when the stack instruction completes processing by the pipeline,
whereby the stack-pointer register contains the only stack pointer, wherein stack pointers for instructions in the pipeline are not stored.

6 more elements

Dependencies are inferred from the claim text.

Stack push/pop tracking and pairing in a pipelined processor

Life of this patent

Stack push/pop tracking and pairing in a pipelined processor

Life of this patent

Abstract

Claims19