Semiconductor process, power supply and temperature compensated system bus integrated interface architecture with precision receiver

An I/O bus interface cell, comprising:

• a driver circuit having an input terminal fed by a logic signal, said driver circuit also having an output terminal, said driver further comprising:
• means, including a pair of series coupled transistors, for providing a first reference voltage responsive to a second reference voltage signal, said second reference voltage signal being equal to the voltage required at the output of the driver in accordance with a load coupled to said driver;
• means, responsive to said first reference voltage, for providing a selectable rise time of a signal driven from said driver, with said first reference voltage corresponding to a voltage required to provide a desired current from the driver over a fixed period of time when the driver is driving said signal;
• means, responsive to said first reference voltage, for providing a selectable fall time of said signal driven from said driver;
• means for providing a selectable impedance characteristic at said terminal of said termination, including means for continuously adjusting said selectable impedance responsive to said second reference voltage, said second reference voltage being provided to an input of said termination circuit;
• and
• a receiver circuit having an input terminal coupled to said output terminal of said driver.

An I/O bus interface cell, comprising:

• a driver circuit having an input terminal fed by a logic signal, said driver circuit also having an output terminal;
• a receiver circuit having an input terminal coupled to said output terminal of said driver, said receiver comprising:
• means, connected directly to a terminal of the I/O cell, for latching a signal provided at said terminal of, said cell;
• means, coupled to said latching means for providing a logic output signal from said receiver circuit;
• a termination circuit having a terminal connected to the output of said driver;
• means, including a pair of series coupled transistors, for providing a first reference voltage responsive to a second reference voltage signal, said second reference voltage signal being equal to the voltage required at the output of the driver in accordance with a load coupled to said driver;
• said termination circuit including means, responsive to said second reference voltage, for providing a selectable impedance, including means for continuously adjusting said selectable impedance in accordance with said second reference voltage;
• means, responsive to said first reference voltage, for providing a selectable rise time of a signal driven from said driver, with said first reference voltage corresponding to a voltage required to provide a desired current from the driver over a fixed period of time when the driver is driving said signal.

A bus system for a computer system, comprising:

• a plurality of bus interface circuits, each of said circuits interfacing an associated device to a bus, with each of said bus interface circuits comprising:
• means for providing a first reference voltage corresponding to a desired impedance level;
• and
• means for providing a second reference voltage corresponding to a desired rise time and fall time to a signal from the cell;
• a corresponding plurality of I/O cells, said cells corresponding to a number of bus lines in a bus, each of said cells, comprising:
• a driver circuit having an input terminal fed by a logic signal, said driver circuit also having an output terminal, and
• means, responsive to said second reference voltage for providing an output current in a fixed period of time from said driver;
• a receiver circuit having an input terminal coupled to said output terminal of said driver;
• and
• a termination circuit having a selectable impedance characteristic at an output terminal thereof, including means for continuously adjusting said selectable impedance characteristic in accordance with said first reference voltage provided to an input thereof, with said termination circuit having said output connected to the input of said receiver circuit .