Information handling system including a data bus management unit, an address management unit for isolating processor buses from I/O and memory
AssigneeInternational Business Machines Corporation
InventorsJohn Michael Kaiser, Warren Edward Maule
Life of this patent
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Abstract
An information handling system includes one or more processing units, a data bus management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, to the I/O bus, and one or more I/O controllers, where the address and data management units isolate the processor buses from the I/O bus and the memory system.
Claims10
An information handling system, comprising:
- at least one processor, each processor having data inputs and outputs and address inputs and outputs;
- a processor data bus, connected to the data inputs and outputs of each processor, said processor data bus operating at a first clock frequency;
- a processor address bus, connected to the address inputs and outputs of each processor;
- a data management unit, connected to the processor data bus, for controlling data flow to and from the processor data bus;
- an address management unit, connected to the processor address bus and to an I/O bus, for controlling address information between the processor address bus and the I/O bus, the address management unit comprising;
- means for decoding addresses and commands from the processor bus;
- means for decoding addresses and commands from the I/O bus;
- means for queuing commands decoded from the processor bus;
- means for queuing commands decoded from the I/O bus;
- first command execution logic for generating commands directed to the processor bus;
- second command execution logic for generating commands directed to the I/O bus;
- and
- means for generating control signals for controlling data and address transmission between the processor bus and the I/O bus;
- a memory system having data and address inputs and outputs, the data I/O of the memory system being connected to the data management unit, and the address I/O of the memory system being connected to the address management unit;
- an said I/O bus having data lines connected to the data management unit, and address lines connected to the address management unit, said I/O bus operating at a second clock frequency;
- and
- at least one I/O controller connected to the I/O bus and to at least one I/O device.
An address management unit, connected to at least a first bus and a second bus, for controlling address and data transmission between the first bus and the second bus, comprising:
- means for decoding addresses and commands from said first bus;
- means for decoding addresses and commands from said second bus;
- means for queuing commands decoded from said first bus;
- means for queuing commands decoded from said second bus;
- first command execution logic for generating commands directed to said first bus;
- second command execution logic for generating commands directed to said second bus;
- and
- means for generating control signals for controlling data and address transmission between said first bus and said second bus.
A bus isolation unit, connected to at least a first bus and a second bus, for controlling transfer of data and address information between the first and second buses in an information handling system, comprising:
- a plurality of buffer registers for buffering data signals from said first bus, data signals from said second bus, and control signals;
- control logic for controlling data flow between said first bus, and said second bus;
- means for decoding addresses and commands from said first bus;
- means for decoding addresses and commands from said second bus;
- means for queuing commands decoded from said first bus;
- means for queuing commands decoded from said second bus;
- first command execution logic for generating commands directed to said first bus;
- second command execution logic for generating commands directed to said second bus;
- and
- means for generating said control signals for controlling data and address transmission between said first bus and said second bus.
Dependencies are inferred from the claim text.