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AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, John Michael Kaiser, William Kurt Lewchuk, Michael Scott Allen
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An efficient multiprocessor address transfer mechanism is utilized within a data processing system including a plurality of bus devices. The present invention places control of the flow of address bus operations within the system controller rather than the bus devices, e.g., a master processor. The system controller issues an address bus grant, in response to an address bus request from a particular bus device, and shortly after that issues another signal notifying the granted bus device that it must now disable the address bus. Furthermore, upon receipt of the signal indicating disablement of the address bus, other bus devices may then snoop, or sample, the address bus.
In a data processing system comprising a plurality of bus devices coupled via a bus, wherein said plurality of bus devices includes one or more processors, and wherein a system controller is coupled to each of said plurality of bus devices, a method comprising the steps of:
A data processing system comprising a plurality of bus devices coupled via a bus, wherein said plurality of bus devices includes one or more processors, and wherein a system controller is coupled to each of said plurality of bus devices, said system controller further comprising:
In a data processing system comprising a plurality of bus devices and a system memory coupled via an address bus, wherein said plurality of bus devices includes one or more processors, and wherein a system controller is coupled to each of said plurality of bus devices, a method comprising the steps of issuing an address bus grant to one of said plurality of bus devices, said address bus grant issued from said system controller to said one of said plurality of bus devices, said address bus grant issued in response to a bus request received by said system controller from said one of said plurality of bus devices;
Dependencies are inferred from the claim text.