US 5,687,289 AGranted

Circuit and method for determining membership in a set during a fuzzy logic operation

AssigneeMotorola, Inc.

InventorsJ. Greg Viot, James M. Sibigtroth

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Abstract

A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. If a membership function has a boundary with an infinite slope, the slope value is set equal to zero and the degree of membership is then set equal to a saturation value for those input values corresponding to the infinite slope boundary.

Claims17

Dependent claims

A method for performing a fuzzy logic operation in a data processing system, the fuzzy logic operation determining membership of an input value in a predetermined membership set which is defined by a plurality of boundary values, wherein one or more of the plurality of boundary values may represent an infinite slope boundary of the predetermined membership set, the method comprising the steps of:

storing in the data processing system a value of zero for the one of the plurality of boundary values representing the infinite slope boundary of the predetermined membership set;
inputting a membership evaluation instruction to a decoder in the data processing system, initiating execution of the fuzzy logic operation in the data processing system based on the membership evaluation instruction being;
decoding the membership evaluation instruction to provide a plurality of control signals, the membership evaluation instruction being decoded by the decoder;
subtracting a first one of the plurality of boundary values from the input value to produce a first delta value in response to a first one of the plurality of control signals, an arithmetic logic means being coupled to the decoder for receiving the first one of the plurality of control signals, the arithmetic logic means being used to subtract the first one of the plurality of boundary values from the input value;
concurrently subtracting the input value from a second one of the plurality of boundary values to produce a second delta value in response to a second one of the plurality of control signals, the arithmetic logic means being coupled to the decoder for receiving the second one of the plurality of control signals, the arithmetic logic means being used to subtract the input value from the second one of the plurality of boundary values;
multiplying the first delta value and a third one of the plurality of boundary values to provide a first result in response to a third one of the plurality of control signals, the arithmetic logic means being coupled to the decoder for receiving the third one of the plurality of control signals, the arithmetic logic means multiplying the first delta value and the third one of the plurality of boundary values;
concurrently multiplying the second delta value and a fourth one of the plurality of boundary values to provide a second result in response to a fourth one of the plurality of control signals, the arithmetic logic means being coupled to the decoder for receiving the fourth one of the plurality of control signals, the arithmetic logic means multiplying the second delta value and the fourth one of the plurality of boundary values, wherein either one or both of the third one and the fourth one of the plurality of boundary values is equal to the value of zero stored in the data processing system for the one of the plurality of boundary values representing the infinite slope boundary of the predetermined membership set;
and
inputting a degree of membership signal using a select logic means, the degree of membership signal indicating that the input value is not included in the predetermined membership set when one of the first delta value and the second delta value is less than zero, the degree of membership signal being equal to a minimum value of one of the first result, the second result, and a fifth one of the plurality of boundary values if neither the first delta value nor the second delta value is less than zero and neither (1) the first delta value and the third one of the plurality of boundary values are both equal to zero nor (2) the second delta value and the fourth one of the plurality of boundary values are both equal to zero, the degree of membership being equal to the fifth one of the plurality of boundary values when either (1) the first delta value and the third one of the plurality of boundary values are both equal to zero or (2) the second delta value and the fourth one of the plurality of boundary values are both equal to zero, the select logic means being coupled to the arithmetic logic means for receiving the first delta value, the second delta value, the first result, and the second result.

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A data processing system for performing a fuzzy logic operation, the fuzzy logic operation determining membership of an input point in a predetermined membership set defined by a plurality of boundary values, wherein one of the plurality of boundary values represents an infinite slope boundary of the predetermined membership set, the data processing system comprising:

input means for receiving a membership evaluation instruction for initiating execution of the fuzzy logic operation in the data processing system, the input means also receiving the input point;
instruction decode means for decoding the membership evaluation instruction to provide a plurality of control signals, the instruction decode means coupled to the input means for receiving the membership evaluation instruction;
memory means for storing and providing the plurality of boundary values, including a value of zero for the one of the plurality of boundary values representing the infinite slope boundary of the predetermined membership set;
a register for storing a plurality of delta values during execution of the fuzzy logic operation;
an arithmetic logic circuit coupled to the memory means for selectively receiving each of the plurality of boundary values, the arithmetic logic circuit coupled to the input means for receiving the input point, the arithmetic logic circuit coupled to the instruction decode means for receiving a portion of the plurality of control signals, the arithmetic logic circuit coupled to the register for receiving a portion of the plurality of delta values, the arithmetic logic circuit generating one of a first and a second delta value and a first and a second product;
and
a result selector having a first input coupled to the arithmetic logic circuit for receiving the first delta value, a second input coupled to the arithmetic logic circuit for receiving the second delta value, a third input coupled to the arithmetic logic circuit for receiving the first product, a fourth input coupled to the arithmetic logic circuit for receiving the second product, and a fifth input for receiving a fifth one of the plurality of boundary values, the result selector providing a degree of membership signal, the degree of membership signal indicating the input point is not included in the predetermined membership set when one of the first delta value and the second delta value is less than zero, the degree of membership signal being equal to a minimum value of one of a first result, a second result, and the fifth one of the plurality of boundary values if neither the first delta value or the second delta value is less than zero and neither (1) the first delta value and the third one of the plurality of boundary values are both equal to zero nor (2) the second delta value and the fourth one of the plurality of boundary values are both equal to zero, the degree of membership being equal to the fifth one of the plurality of boundary values when either (1) the first delta value and the third one of the plurality of boundary values are both equal to zero or (2) the second delta value and the fourth one of the plurality of boundary values are both equal to zero.

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Dependencies are inferred from the claim text.

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Abstract

storing in the data processing system a value of zero for the one of the plurality of boundary values representing the infinite slope boundary of the predetermined membership set;
inputting a membership evaluation instruction to a decoder in the data processing system, initiating execution of the fuzzy logic operation in the data processing system based on the membership evaluation instruction being;
decoding the membership evaluation instruction to provide a plurality of control signals, the membership evaluation instruction being decoded by the decoder;
subtracting a first one of the plurality of boundary values from the input value to produce a first delta value in response to a first one of the plurality of control signals, an arithmetic logic means being coupled to the decoder for receiving the first one of the plurality of control signals, the arithmetic logic means being used to subtract the first one of the plurality of boundary values from the input value;
concurrently subtracting the input value from a second one of the plurality of boundary values to produce a second delta value in response to a second one of the plurality of control signals, the arithmetic logic means being coupled to the decoder for receiving the second one of the plurality of control signals, the arithmetic logic means being used to subtract the input value from the second one of the plurality of boundary values;
multiplying the first delta value and a third one of the plurality of boundary values to provide a first result in response to a third one of the plurality of control signals, the arithmetic logic means being coupled to the decoder for receiving the third one of the plurality of control signals, the arithmetic logic means multiplying the first delta value and the third one of the plurality of boundary values;
concurrently multiplying the second delta value and a fourth one of the plurality of boundary values to provide a second result in response to a fourth one of the plurality of control signals, the arithmetic logic means being coupled to the decoder for receiving the fourth one of the plurality of control signals, the arithmetic logic means multiplying the second delta value and the fourth one of the plurality of boundary values, wherein either one or both of the third one and the fourth one of the plurality of boundary values is equal to the value of zero stored in the data processing system for the one of the plurality of boundary values representing the infinite slope boundary of the predetermined membership set;
and
inputting a degree of membership signal using a select logic means, the degree of membership signal indicating that the input value is not included in the predetermined membership set when one of the first delta value and the second delta value is less than zero, the degree of membership signal being equal to a minimum value of one of the first result, the second result, and a fifth one of the plurality of boundary values if neither the first delta value nor the second delta value is less than zero and neither (1) the first delta value and the third one of the plurality of boundary values are both equal to zero nor (2) the second delta value and the fourth one of the plurality of boundary values are both equal to zero, the degree of membership being equal to the fifth one of the plurality of boundary values when either (1) the first delta value and the third one of the plurality of boundary values are both equal to zero or (2) the second delta value and the fourth one of the plurality of boundary values are both equal to zero, the select logic means being coupled to the arithmetic logic means for receiving the first delta value, the second delta value, the first result, and the second result.

6 more elements