US 5,687,203 A · Digital phase locked loop circuit

Abstract

A digital PLL circuit has a data sampling circuit for sampling input data in response to N phase clocks in the direction of time. The phase of the clock corresponding to, among the sampled data, the data in which edges are evenly detected is used as a first phase or reference clock. The successive clocks following the first phase clock are used as a second phase clock to an N-th phase clock. The sampled data are rearranged in synchronism with the first phase clock to the N-th phase clock to turn out first phase to N-th phase sampled data. The first phase to the N-th phase sampled data are latched by the first phase clock. The pattern of data received in bursts is identified every period on the basis of the latched first to N-th phase data. Among the latched first to N-th sampled data, the data to be identified are selected. These data are retimed in synchronism with the first phase clock so as to output a phase clock signal.

Claims6

Dependent claims

A digital PLL circuit comprising:

sampling means for sampling a burst data signal in synchronism with N phase clocks to thereby output N phase sampled data signals;
rearranging means for rearranging the N phase sampled data signals in synchronism with a reference signal to thereby generate N phase rearranged data signals;
select signal generating means for generating a select signal;
selecting means for selecting, in response to said select signal, an optimal sampled data signal out of said N phase rearranged signals;
and
retiming means for retiming said sampled data signal selected in synchronism with said reference signal.

3 more elements

A digital PLL circuit comprising:

clock selecting means for selecting one of N phase clocks, which are identical in frequency with a burst data signal and sequentially shifted in phase by 360 degrees/N (N being 2 or greater integer), at a time in response to a select signal indicative of which of the N phase clocks should be selected:
sampling means for sampling the burst data signal in response to said N phase clocks to thereby generate N sampled data:
rearranging means for rearranging, by using the clock indicated by said select signal as a reference first phase clock and using the successive clocks as a second phase-clock to an N-th phase clock, the N sampled data in response to said first phase clock to said N-th clock to thereby output a first phase sampled data to an N-th phase sampled data;
latching means for latching said first sampled data to said N-th sampled data in response to said reference first phase clock separated;
edge detecting means for detecting, based on levels of nearby phases output from said latching means, a position of the phase where a negative-going edge exists to thereby generate negative-going edge position information every period of said clock, and for detecting a number of negative-going edges and a number of positive-going edges to thereby generate negative-going edge number information and positive-going edge number information every period of said clock;
calculating means for calculating a mean value of said negative-going edge position information from the past to the present every period to thereby output said select signal;
data selecting means for selecting one of said first phase sampled data to said N-th phase sampled data at a time every period on the basis of said first phase sampled data to said N-th phase sampled data and said negative-going edge number information and said positive-going edge number information;
and
retiming means for retiming outputs of said data selecting means in synchronism with said first phase clock.

6 more elements

Dependencies are inferred from the claim text.

Digital phase locked loop circuit

Life of this patent

Digital phase locked loop circuit

Life of this patent

Abstract

Claims6