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US 5,687,202 AGranted
Programmable phase shift clock generator
AssigneeCyrix Corporation
InventorJohn K. Eitrheim
Life of this patent
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Abstract
A programmable phase shift clock generator is disclosed including a phase comparator, an up-down counter, a ring oscillator, and an adjustable delay line for determining a digital signature of an input clock and precisely generating a phase shifted clock signal.
Claims15
A programmable phase shift clock generator comprising:
- (a) a phase comparator having a first input coupled to receive an input clock signal, a second input coupled to receive a feedback signal, and an output to provide a difference between the input clock signal and the feedback signal;
- (b) an up-down counter having an input coupled to the output of the phase comparator and an output to provide an n-bit count;
- (c) a ring oscillator having an n-bit input coupled to the output of the up-down counter and an output to provide a loop clock output signal, the loop clock output signal being coupled as the feedback signal to the second input on the phase comparator;
- (d) an adjustable delay line having an input coupled to receive the loop clock output signal, at least n-1-bit control inputs coupled to the output of the up-down counter, and an output to provide a phase shifted clock signal;
- (e) a divider interposed between the output of the ring oscillator and the second input of the phase comparator;
- (f) wherein the ring oscillator comprises an adjustable delay line having an input and an output and an inverter coupled therebetween;
- and;
- (g) wherein the adjustable delay line (d) has n-bit control inputs and further comprises an arithmetic divider interposed between the output of the up-down counter and the n-bit control inputs.
5 more elements
A programmable phase shift dock generator comprising:
- (a) phase comparator means for comparing an input clock signal to a feedback signal and for generating a difference output therebetween;
- (b) up-down counter means, responsive to the difference output from the phase comparator means, for generating an n-bit error count;
- (c) ring oscillator means, responsive to the n-bit error count from the up-down counter means, for generating a loop dock output signal;
- and,
- (d) adjustable delay line means, coupled to the ring oscillator means and the up-down counter means, for generating a phase shifted clock signal
- (e) divider means, interposed between the ring oscillator means and the phase comparator means, for scaling the clock output signal;
- (f) wherein the ring oscillator means comprises an adjustable delay line having an input and an output and an inverter coupled therebetween;
- and,
- (g) wherein the adjustable delay line means (d) has n-bit control inputs and further comprises arithmetic divider means, interposed between the up-down counter means and the n-bit control inputs, for adjusting a duty cycle of the phase shifted clock signal.
6 more elements
A method of generating a programmable phase shift clock comprising the steps of:
- (a) comparing an input dock signal to a feedback signal and generating a difference output therebetween;
- (b) generating an n-bit error count in response to step (a);
- (c) responsive to step (b), generating a loop clock output signal to an adjustable delay line and providing the loop clock output signal as the feedback signal in step (a);
- (d) generating a phase shifted clock signal response to steps (b) and (c);
- (e) dividing the loop clock output signal in step (c) before providing the loop clock output signal as the feedback signal in step (a)
- (f) wherein step (c) comprises the step of feeding back the inversion of an output from an adjustable delay line to an input on the adjustable delay line;
- and,
- (g) arithmetically dividing the n-bit error count in step (b) to adjust a duty cycle of the phase shifted clock signal in step (d).
5 more elements
A programmable phase shift clock generator comprising:
- (a) a delay line loop clock generator having a loop clock output and a plurality of error count bits;
- and,
- (b) an adjustable delay line having an input coupled to receive the loop clock output, and a plurality of control inputs coupled to at least some of the plurality of error count bits, and an output to provide a phase shifted clock signal;
- and,
- (c) an arithmetic divider interposed between the plurality of error count bits and the plurality of control inputs to program a phase shift into the phase shifted clock signal.
2 more elements
Dependencies are inferred from the claim text.