Non-coherent direct sequence spread spectrum receiver for detecting bit/symbol chip sequences using threshold comparisons of chip sequence correlations

A method for recovering a digital signal comprising a sequence of bits having a first and second state from a direct sequence spread spectrum binary phase shift keyed (BPSK) signal wherein each bit in the first state is substituted by a first chip sequence and each bit in the second state is substituted by a second chip sequence, the method comprising the steps of:

• demodulating the direct sequence spread spectrum BPSK signal to form an in-phase baseband signal and a quadrature-phase baseband signal;
• correlating the in-phase baseband signal with the first and second chip sequences to generate a first and a second correlation value respectively;
• correlating the quadrature-phase baseband signal with the first and second chip sequence to generate a third and a fourth correlation value respectively;
• comparing each correlation value to a corresponding threshold value;
• responsive to either of the first and third correlation values being greater than the corresponding threshold values, indicating a first bit state detection;
• and
• responsive to either of the second and fourth correlation values being greater than the corresponding threshold values, indicating a second bit state detection.

A method for recovering a digital signal comprising a sequence of interleaved I-Channel and Q-Channel bits, each having a first and second state, from a direct sequence spread spectrum quadrature phase shift keyed (QPSK) signal wherein each I-Channel bit in the first state is substituted by a first chip sequence, each I-Channel bit in the second state is substituted by a second chip sequence, each Q-Channel bit in the first state is substituted by a third chip sequence and each Q-Channel bit in the second state is substituted by a fourth chip sequence, the method comprising the steps of:

• demodulating the direct sequence spread spectrum QPSK signal to form an in-phase baseband signal and a quadrature-phase baseband signal;
• correlating the in-phase baseband signal with the first, second, third and fourth chip sequences to generate a first, a second, a third and a fourth correlation value respectively;
• correlating the quadrature-phase baseband signal with the first, second, third and fourth chip sequences to generate a fifth, a sixth, a seventh and an eighth correlation value respectively;
• comparing each correlation value to a corresponding threshold value;
• responsive to any of the first, third, fifth, or seventh correlation values being greater than the corresponding threshold values, indicating a first bit state detection;
• and
• responsive to any of the second, fourth, sixth, or eighth correlation values being greater than the corresponding threshold values, indicating a second bit state detection.

A method for transmitting and receiving a digital signal comprised of bits having first and second states, the method comprising the steps of:

• substituting each bit having the first state with a first chip sequence and substituting each bit having a second state with a second chip sequence, to form a spread spectrum signal;
• phase modulating a carrier wave with the spread spectrum signal to form a BPSK signal;
• transmitting the BPSK signal;
• receiving the transmitted BPSK signal;
• mixing the received BPSK signal with a first sinusoid having substantially the same frequency as the carrier wave to form an in-phase baseband signal;
• mixing the received BPSK signal with a second sinusoid having substantially the same frequency as the carrier wave and having a 90 degree phase shift relative to the first sinusoid to form a quadrature-phase baseband signal;
• correlating the in-phase baseband signal with the first and second chip sequences to generate a first and a second correlation value respectively;
• correlating the quadrature-phase baseband signal with the first and second chip sequence to generate a third and a fourth correlation value respectively;
• comparing each correlation value to a corresponding threshold value;
• responsive to either of the first and third correlation values being greater than the corresponding threshold values, indicating a first bit state detection;
• and
• responsive to either of the second and fourth correlation values being greater than the corresponding threshold values, indicating a second bit state detection.

An apparatus for recovering an information signal from a digitized BPSK direct sequence spread spectrum signal having been downconverted by a non-coherent demodulator to form an in-phase signal on an in-phase channel and a quadrature-phase signal on a quadrature channel, the direct sequence spread spectrum signal being spread using a plurality of chip sequences, the apparatus comprising:

• a bank of matched filters having a first plurality of inputs coupled to the in-phase channel and a second plurality of inputs coupled to the quadrature-phase channel, and having a plurality of outputs each having one of a plurality of states responsive to the degree of correlation between an associated input and an associated chip sequence;
• a bank of threshold comparators each associated with a chip sequence, the bank having a plurality of inputs coupled to the plurality of matched filter outputs and a plurality of corresponding outputs each having a first state responsive to the corresponding input being greater than a predetermined value and a second state responsive to the corresponding input being less than a predetermined value;
• a recovery circuit having a plurality of inputs coupled to the comparator outputs, the recovery circuit having a clock output being in a first state responsive to any one of the inputs being in the first state and being in a second state responsive to all of the inputs being in the second state, the recovery circuit further having a first symbol output being in a first state responsive to any one of the comparator outputs associated with the first chip sequence being in the first state and being in a second state responsive to each of the comparator outputs associated with the first chip sequence being in second state;
• and
• a bit detection circuit having a plurality of inputs coupled to the recovery circuit outputs and having an output having a first state responsive to the first symbol being in the first state on a clock state transition and having a second state responsive to all of the inputs being in the second state on a clock state transition.

A non-coherent spread spectrum demodulator for coupling to a receiving path and for demodulating a direct sequence spread spectrum signal having a plurality of chip sequences, the demodulator comprising:

• an in-phase mixer having an input and an output, the input coupled to the receiving path for converting the direct sequence spread spectrum signal to an in-phase baseband signal;
• a quadrature-phase mixer having an input and an output, the input coupled to the receiving path for converting the direct sequence spread spectrum signal to a quadrature-phase baseband signal;
• first and second analog-to-digital converters having inputs and outputs, the inputs coupled to the in-phase and quadrature-phase baseband mixer outputs respectively;
• for each chip sequence, a matched filter having the associated chip sequence as a first input, having a second input coupled to the output of the first analog-to-digital converter and having a correlation output;
• for each chip sequence, a matched filter having the associated chip sequence as a first input, having a second input coupled to the output of the second analog-to-digital converter and having a correlation output;
• a plurality of threshold comparators each coupled to a correlation output and each associated with a chip sequence, each threshold comparator having a detect output having a first state responsive to the correlation output being greater than a predetermined value and having a second state responsive to the correlation output being less than the predetermined value;
• for each chip sequence, a symbol detect circuit having a plurality of inputs coupled to the detect outputs of the comparators associated with the chip sequence, symbol detect circuit having an output being in a first state responsive to any one of the inputs being in the first state and being in a second state responsive to all of the inputs being in the second state;
• a bit clock generator having inputs coupled to the symbol detect circuit outputs and having an output in a first state responsive to any of the inputs being in the first state and having a second state responsive to all of the inputs being in the second state;
• and
• a bit generation circuit having an input coupled to the bit clock generator output and a plurality of inputs coupled to the symbol detect circuit outputs for multiplexing the symbol detect circuit outputs.