Serial data input/output method and apparatus
AssigneeTexas Instruments Incorporated
InventorsLee D. Whetsel, Jr., Benjamin H. Ashmore, Jr.
Life of this patent
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Abstract
A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.
Claims50
A data communication interface operable to continuously transfer serial data between a bus controller and a device, comprising:
- a bus for transferring serial data between said bus controller and said device;
- storage circuitry external to said bus controller and having a parallel port coupled to the device and having a serial port;
- interface circuitry having a serial port coupled to said bus operable to transfer serial data between said bus and said serial port of said storage circuitry;
- device access control circuitry operable to automatically transfer multiple parallel data patterns from said storage circuitry to said device responsive to a signal, said device access control circuitry operable to allow serial data input to said storage circuitry to continue without interruption;
- and
- said device access control circuitry selectively operable to automatically transfer multiple parallel data patterns from said device to said storage circuitry responsive to a signal, said device access control circuitry being operable to allow serial data output from said storage circuitry to continue without interruption.
A data communication interface operable to continuously transfer serial data between a memory and a bus controller when enabled to do so by said bus controller, comprising:
- a bus for transferring serial data;
- an input/output register coupled to said bus and operable to selectively input serial data from said bus and output parallel data, and alternatively operable to input parallel data and output serial data onto said bus;
- interface circuitry operable to control data transfer between said bus and said input/output register;
- a memory external to said bus controller and coupled to said input/output register and operable to selectively store parallel data from said input/output register and further operable to output parallel data to said input/output register;
- and
- memory access control circuitry associated with said memory and operable to automatically transfer multiple parallel data patterns between said input/output register and said memory such that serial data can be transferred between the bus and the input/output register automatically, said memory access control circuitry performing said multiple parallel transfers such that the serial data transfer is uninterrupted.
A method of transferring serial data on a bus from a device associated with a target interface circuit to a bus controller, said data passing through a plurality of interface circuits coupled to said bus prior to being input to said bus controller, comprising the steps of:
- transferring data from a storage location in the device into a register associated with the target interface circuit;
- shifting data from the register onto the bus;
- transferring additional data from the storage location in the device into the register after the last data bit is shifted out of the register;
- monitoring the number of data bits shifted from the register onto said bus;
- generating a control signal when a predetermined number of bits have been shifted from said register;
- loading data into the register from said device responsive to said control signal;
- and
- repeating the above steps so that data is continuously output onto the bus.
A method of transferring serial data on a bus from a bus controller to a device associated with a target interface circuit, said data passing through a plurality of interface circuits coupled to said bus prior to being input to said target interface circuit associated with said device, comprising the steps of:
- shifting data from a data source onto the bus and shifting said data sequentially through each interface circuit preceding the target interface circuit;
- monitoring the number of data bits shifted from said data source onto said bus;
- generating a first control signal after a lapse of time indicative of said data from said source passing through said plurality of interface circuits reaching said target interface circuit;
- transferring said shifted data from said bus into a register to a storage location in said target interface circuit responsive to said first control signal;
- generating a second control signal indicative of said register filling with data;
- transferring data from said register to said device responsive to said second control signal;
- and
- repeating said stop of transferring data from said register to said storage location in said device in response to each generated second control signal.
Dependencies are inferred from the claim text.