Synchronous semiconductor memory capable of saving a latency with a reduced circuit scale
AssigneeNEC Corporation
InventorsMichinori Sugawara, Manabu Kawaguchi
Life of this patent
Estimating the term…
Abstract
In a synchronous semiconductor memory having a memory section (MS) for memorizing a particular datum, a single output latch circuit (32) is connected to an output side of the memory section and controlled by the use of a pulse signal whether or not the particular datum is passed through the output latch circuit. The pulse signal is produced in a pulse generator (31) to synchronize with an internal clock signal which is produced in an internal clock signal producing arrangement (21 and 22). The pulse signal has a pulse width which is independent of the internal clock signal and determined dependent on a timing when the memory section outputs the particular datum.
Claims6
A synchronous semiconductor memory including a memory section for memorizing a particular datum, an input section for inputting said particular datum to said memory section, an output section for outputting said particular datum from said memory section, and control means responsive to an external clock signal for synchronously controlling operation of each of said input and said output sections, said control means comprising:
- internal clock signal producing means responsive to said external clock signal for producing an internal clock signal delayed from said external clock signal;
- control signal producing means connected to said internal clock signal producing means and responsive to said internal clock signal for producing an input section control signal which is used in controlling the operation of said input section;
- and
- pulse signal producing means connected to said internal clock signal producing means and responsive to said internal clock signal for producing a pulse signal synchronized with said internal clock signal, said pulse signal having a pulse width which is independent of said internal clock signal and which is determined dependent on a timing when said memory section outputs said particular datum;
- said output section comprising a single output latch circuit which is connected to said memory section and said pulse signal producing means for controlling by the use of said pulse signal whether or not said particular datum is passed through said single output latch circuit.
Dependencies are inferred from the claim text.