Multi-mode cache structure
AssigneesSharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
InventorDieter Spaderna
Life of this patent
Estimating the term…
Abstract
A multimode cache structure includes a predefined block of memory and controls for that block of memory which allow the memory block to perform multiple functions. The selectable, multiple functions include a cache mode, a SRAM mode, a flush mode and an invalidate mode. A control register is defined and is associated with the predefined memory block, which control register includes multiple status bits therein. Each of the status bits corresponds to one of the multiple functions and, when a particular status bit is set, the predefined block of memory performs a function corresponding to the status bit that is set.
Claims12
In an integrated circuit having a CPU, and having a connection to a main memory unit, a multimode cache structure comprising:
- a predefined block of memory which is shiftable between multiple functions, including a cache mode, wherein multiple cache sets, each having multiple cache lines, are stored in said predefined memory block, a SRAM mode, a flush mode and an invalidate mode, and wherein said control register includes designated status bits therein for said cache mode, said SRAM mode, said flush mode and said invalidate mode, and wherein said cache mode, said SRAM mode and said flush mode are mutually exclusive functions;
- and
- a control register associated with said predefined memory block having multiple status bits therein, wherein each of said status bits corresponds to one of said multiple functions, and wherein, with a status bit set, said predefined block of memory performs a function corresponding to the status bit that is set.
In an integrated circuit having a CPU, and having a connection to a main memory unit, a multimode cache structure comprising:
- a predefined block of memory which is shiftable between multiple functions, including a cache mode, wherein multiple cache sets, each having multiple cache lines, are stored in said predefined memory block, a SRAM mode, a flush mode and an invalidate mode, and wherein said control register includes designated status bits therein for said cache mode, said SRAM mode, said flush mode and said invalidate mode, and wherein said cache mode, said SRAM mode and said flush mode are mutually exclusive functions, and wherein said predefined memory block, when in said cache mode, includes a Tag RAM portion and a data RAM portion, and wherein said predefined memory block, when in said SRAM mode, includes a unified storage region;
- and
- a control register associated with said predefined memory block having multiple status bits therein, wherein each of said status bits corresponds to one of said multiple functions, and wherein, with a status bit set, said predefined block of memory performs a function corresponding to the status bit that is set.
Dependencies are inferred from the claim text.