Sense amplifier of semiconductor memory having an increased reading speed

A semiconductor memory comprising at least one pair of signal lines which are complementary to each other, a plurality of memory cells connected to a plurality of word lines, respectively, and also connected to said one pair of signal lines in such a manner that when one of said plurality of word lines is activated, a potential difference corresponding to a content stored in the memory cell connected to the activated word line appears between said one pair of signal lines, and a sense amplifier having a differential amplifier connected to receive said one pair of signal lines to output a signal in accordance with the potential difference appearing between said one pair of signal lines, and a flipflop for amplifying said potential difference appearing between said one pair of signal lines, wherein each of said differential amplifier and said flipflop is formed of bipolar transistors.

A semiconductor memory comprising at least one pair of signal lines which are complementary to each other, a plurality of memory cells connected to a plurality of word lines, respectively, and also connected to said one pair of signal lines in such a manner that when one of said plurality of word lines is activated, a potential difference corresponding to a content stored in the memory cell connected to the activated word line appears between said one pair of signal lines, and a sense amplifier having a differential amplifier connected to receive said one pair of signal lines to output a signal in accordance with the potential difference appearing between said one pair of signal lines, and a flipflop for amplifying said potential difference appearing between said one pair of signal lines, wherein one of said differential amplifier and said flipflop is formed of bipolar transistors, but the other of said differential amplifiers and said flipflop is formed of MOS transistors.

A semiconductor memory at least including one pair of complementary digit lines, a plurality of word lines, a plurality of SRAM memory cells arranged at intersections between said one pair of digit lines and said plurality of word lines, respectively, and also connected to said one pair of signal lines in such a manner that when one of said plurality of word lines is activated, a potential difference corresponding to a content stored in the memory cell connected to the activated word line appears between said one pair of signal lines, first and second bipolar transistors having an emitter connected to each other, means for supplying a signal corresponding to potentials on said one pair of complementary digit lines, to a base of said first and second bipolar transistor, third and fourth bipolar transistors having a collector connected to a base of said first and second bipolar transistors, respectively, and an emitter connected to each other, a base of said third bipolar transistor being connected to the collector of said fourth bipolar transistor, and a base of said fourth bipolar transistor being connected to the collector of said third bipolar transistor, and means for detecting a difference between a collector current of said first bipolar transistor and a collector current of said second bipolar transistor, so as to convert the detected current difference into a voltage.

A semiconductor memory at least including one pair of complementary digit lines, a plurality of word lines, a plurality of SRAM memory cells arranged at intersections between said one pair of digit lines and said plurality of word lines, respectively, and also connected to said one pair of signal lines in such a manner that when one of said plurality of word lines is activated, a potential difference corresponding to a content stored in the memory cell connected to the activated word line appears between said one pair of signal lines, first and second MOS transistors having a source connected to each other, means for supplying a signal corresponding to potentials on said one pair of complementary digit lines, to a gate of said first and second MOS transistors, first and second bipolar transistors having a collector connected to a gate of said first and second MOS transistors, respectively, and an emitter connected to each other, a base of said first bipolar transistor being connected to the collector of said second bipolar transistor, and a base of said second bipolar transistor being connected to the collector of said first bipolar transistor, and means for detecting a difference between a drain current of said first MOS transistor and a drain current of said second MOS transistor, so as to convert the detected current difference into a voltage.

A semiconductor memory at least including one pair of complementary digit lines, a plurality of word lines, a plurality of SRAM memory cells arranged at intersections between said one pair of digit lines and said plurality of word lines, respectively, and also connected to said one pair of signal lines in such a manner that when one of said plurality of word lines is activated, a potential difference corresponding to a content stored in the memory cell connected to the activated word line appears between said one pair of signal lines, first and second bipolar transistors having an emitter connected to each other, means for supplying a signal corresponding to potentials on said one pair of complementary digit lines, to a base of said first and second bipolar transistor, first and second MOS transistors having a drain connected to a base of said first and second bipolar transistors, respectively, and a source connected to each other, a gate of said first MOS transistor being connected to the drain of said second MOS transistor, and a gate of said second MOS transistor being connected to the drain of said first MOS transistor, and means for detecting a difference between a collector current of said first bipolar transistor and a collector current of said second bipolar transistor, so as to convert the detected current difference into a voltage.