Flash EEPROM worldline decoder

A method of manufacturing a flash memory wordline decoder comprising the steps of:

• forming a plurality of voltage terminals to receive a plurality of voltages;
• forming a plurality of address terminals to receive a plurality of address signals;
• forming a procedure terminal to receive a procedure signal;
• forming a plurality of output wordlines adapted to be coupled to a bank of flash transistors;
• and
• forming a decoder circuit couple to said voltage terminals, said address terminals and said procedure terminal and configured to decode said address signals, said decoder circuit including a latch circuit coupled to said wordlines and configured to selectively latch a random set of wordlines and to simultaneously provide an operational voltage on said set of wordlines to accomplish a predetermined operation responsive to said procedure signal.

A method of retrieving information from a flash memory having a plurality of wordlines and a wordline latch circuit coupled to said wordlines, said method comprising the steps of:

• receiving a plurality of voltages;
• receiving a plurality of address signals;
• receiving a procedure signal;
• decoding said address signals;
• selectively latching a random set of wordlines corresponding to aid address signals;
• and,
• simultaneously providing an operational voltage on said set of wordlines to accomplish a predetermined operation responsive to said procedure signal.