PMOS memory cell with hot electron injection programming and tunnelling erasing

A method of programming a floating gate P-channel memory cell having a P+ source and a P+ drain formed in an N-type well region, said method comprising the steps of:

• applying a first bias voltage to said P+ source and to said N-type well region of said cell;
• applying a second bias voltage to said P+ drain;
• applying a third bias voltage to a control gate of said cell to cause the acceleration of holes across a channel region extending between said P+ source and said P+ drain, said holes colliding with electrons in a depletion region of said P+ drain to result in the generation of hot electrons via impact ionization, said hot electrons being injected into said floating gate, thereby negatively charging said floating gate, wherein said first bias voltage is between approximately 5 and 15 volts, said second bias voltage is between approximately 0 and 2 volts, and said third bias voltage is between approximately 5 and 16 volts.

A method of programming a floating gate P-channel memory cell having a P+ source and a P+ drain formed in an N-type well region, said method comprising the steps of:

• applying a first bias voltage to said P+ source and to said N-type well region of said cell;
• applying a second bias voltage to said P+ drain;
• applying a third bias voltage to a control gate of said cell to cause the acceleration of holes across a channel region extending between said source and said drain, said holes colliding with electrons in a depletion region of said drain to result in the generation of hot electrons via impact ionization, said hot electrons being injected into said floating gate, thereby negatively charging said floating gate, wherein said first bias voltage is between approximately 5 and 15 volts, said second bias voltage is between approximately 0 and 2 volts, and said third bias is a ramped voltage increasing from approximately 0 volts to as high as approximately 16 volts.

A method of erasing a floating gate P-channel memory cell having a P+ source and a P+ drain formed in an N-type well, said method comprising the steps of:

• applying a first bias voltage to a source and said well of said cell;
• applying a second bias voltage to said drain;
• applying a third bias voltage to a control gate of said cell to cause the tunneling of electrons from said floating gate to said N-type well, to said P+ source, and to said P+ drain of said cell, thereby discharging said floating gate.