Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell

In an integrated circuit having an array of memory cells, each memory cell storing a plurality of bits, each memory cell having first and second terminals and a control terminal, a circuit for reading said plurality of bits comprising:

• a bias current reference;
• multiplexer circuits responsive to address signals for connecting a selected memory cell in said array to said bias current reference;
• and
• a voltage comparator connected to a node between said second terminal of said selected memory cell and said bias current reference, said voltage comparator further connected to a reference voltage for comparing a voltage at said node and said reference voltage to determine a bit stored in said memory cell.

In an integrated circuit having an array of memory cells, a circuit for programming an amount of charge in a selected memory cell corresponding to a plurality of bits, said circuit comprising

• a high voltage circuit for generating a high voltage for programming memory cells;
• a voltage comparator connected to said selected memory cell and a reference voltage for comparing a voltage corresponding to said amount of charge stored in said selected memory cell and said reference voltage;
• and
• a programming circuit connected to said high voltage circuit and said voltage comparator, said programming circuit in response to said voltage comparator engaging said high voltage circuit to program said selected memory cell until said voltage corresponding to said amount of charge stored in said selected memory cell matches said reference voltage.

In an integrated circuit having an array of memory cells, each memory cell capable of storing multiple bits of information, a plurality of latches connected to said array of memory cells, said latches organized into a first bank and a second bank;

• and
• at least one data terminal, a method of operating said integrated circuit comprising alternately coupling said first bank to said array of memory cells and said second bank to said one data terminal, and said second bank to said array of memory cells and said first bank to said one data terminal;
• and
• simultaneously transferring data between one bank of latches and said array of memory cells, and transferring data between another bank of latches and said data terminal for faster read and write operations.

In an integrated circuit having an array of memory cells, each memory cell having first and second terminals and a control terminal, each memory cell storing a plurality of bits, a method for reading said plurality of bits in a memory cell, comprising connecting said first terminal of said memory cell to a first voltage source;

• connecting said control terminal of said memory cell to a voltage source to electrically couple said second terminal to said first terminal;
• connecting said second terminal to a bias current circuit, said bias current circuit generating a fixed bias current through said second terminal;
• and
• connecting said second terminal to a circuit for sensing a voltage at said second terminal relative to a predetermined reference voltage and generating a digital output corresponding to said sensed voltage at said second terminal.

An integrated circuit comprising

• an array of memory cells, each memory cell capable of holding a voltage corresponding to a plurality of bits, said array organized into blocks, each block having reference memory cells and data memory cells;
• voltage generation circuits generating first and second sets of reference voltage levels;
• and
• programming circuits simultaneously setting voltages in said data memory cells with respect to said first set of reference voltage levels, said voltages corresponding to data bits, and setting said second set of reference voltage levels in said reference memory cells.

An integrated circuit comprising

• an array of memory cells, each memory cell capable of holding a voltage corresponding to a plurality of bits, said array organized into blocks, each block having reference memory cells and data memory cells;
• voltage generation circuits generating a set of reference voltage levels;
• and
• programming circuits setting said set of reference voltage levels in said reference memory cells and setting voltages in said data memory cells with respect to said set of reference voltage levels, said voltages corresponding to data bits.

A method of operation in an integrated circuit having an array of memory cells, each memory cell capable of holding a voltage corresponding to a plurality of bits, said array having reference memory cells and data memory cells, said method comprising

• receiving pluralities of data bits;
• programming voltages in said data memory cells with reference to a first set of reference voltage levels, each voltage corresponding to a plurality of data bits;
• and
• simultaneously programming a second set of reference voltage levels in said reference memory cells.

A method of operation in an integrated circuit having an array of memory cells, each memory cell capable of holding a voltage corresponding to a plurality of bits, said array having reference memory cells and data memory cells, said method comprising

• receiving pluralities of data bits;
• programming a set of reference voltage levels in said reference memory cells;
• and
• programming voltages in said data memory cells with reference to said set of reference voltage levels, each voltage corresponding to a plurality of data bits.

An integrated circuit comprising

• an array of memory cells, each memory cell capable of holding a voltage corresponding to a plurality of bits, said array organized into blocks, each block having reference memory cells and data memory cells;
• voltage generation circuits generating first and second sets of reference voltage levels;
• programming circuits simultaneously setting voltages with respect to said first set of reference voltage levels in said data memory cells, said voltages corresponding to data bits, and setting a second set of reference voltage levels in said reference memory cells;
• and
• reading circuits selectively comparing voltages set in said data memory cells with respect to said second set of reference voltage levels in said reference memory cells to determine data bits corresponding to said set voltages in said data memory cells, and with respect to said first set of reference voltage levels to operate with said programming circuits to set voltages with respect to said first set of reference voltage levels in said data memory cells.

An integrated circuit comprising an array of memory cells, each memory cell capable of holding a voltage corresponding to a plurality of bits, said array organized into blocks, each block having reference memory cells and data memory cells;

• voltage generation circuits generating a set of reference voltage levels;
• programming circuits setting said set of reference voltage levels in said reference memory cells and setting voltages with respect to said set of reference voltage levels in said data memory cells, said voltages corresponding to data bits;
• and
• reading circuits selectively comparing voltages set in said data memory cells with respect to said set of reference voltage levels in said reference memory cells to determine data bits corresponding to said set voltages in said data memory cells and to operate with said programming circuits to set voltages with respect to said set of reference voltage levels in said data memory cells.