Power bussing layout for memory circuits

A memory circuit comprising:

• a plurality of memory arrays stacked along a first direction, each memory array comprising:
• a plurality of parallel rows of memory cells coupled to a plurality of parallel polysilicon word lines, respectively, said plurality of polysilicon word lines extending in a second direction perpendicular to said first direction, and
• a plurality of first layer metal word lines corresponding to, and extending in parallel with said plurality of polysilicon word lines, and respectively making contact to said plurality of polysilicon word lines at a plurality of contact regions, such that said plurality of contact regions divide each row of memory cells into a corresponding plurality of segments;
• a plurality of sense amplifiers disposed between, and coupled to an adjacent one of said plurality of memory arrays;
• and
• power bus lines made of said second layer metal extending in said first direction cross said plurality of memory arrays over a plurality of areas defined by said contact regions,
• wherein, said plurality of first layer metal word lines terminate at a last one of said plurality of contact regions, leaving a last segment of each of said plurality of polysilicon word lines without a corresponding parallel first layer metal line, and
• wherein, a wide first metal layer bus line is disposed over said last segment of each of said plurality of polysilicon word lines in each memory array.