Net list for use in logic simulation and back annotation method of feedbacking delay information obtained through layout design to logic simulation

A back annotation method of feedbacking a wiring delay after layout to logic simulation, comprising the steps of:

• extracting, for each node connection, a capacitance relating to said node connection from the layout;
• calculating, for each node connection corresponding to a specific wire having a capacitive coupling between a different wire and itself, a time constant (Rd.times.Cc) which is a product of the impedance (Rd) of a logic cell for driving said specific wire and the coupled capacitance (Cc) which is a capacitance resulting from said capacitive coupling and a capacitance ratio (Cc/Ct) which is a ratio of the coupled capacitance (Cc) to a total capacitance (Ct) relating to said specific wire;
• and
• adding, for each node connection in which the time constant (Rd.times.Cc) exceeds a specified first threshold value or the capacitance ratio (Cc/Ct) exceeds a specified second threshold value, to a net list, a delay adding means for selectively adding a delay to the logic output of a logic cell provided in said node connection so as to drive said node connection by means of a control input and a virtual connection for capacitive coupling for transmitting, to said delay adding means, the logic output of a logic cell for driving a node connection corresponding to said different wire as said control input.

A netlist for use in logic simulation comprising:

• logic cells;
• node connections for connecting between the respective logic cells:
• delay adding means, provided at one of said node connections which corresponds to one wire having a coupled capacitance between a different wire and itself, said delay adding means being provided for adding a delay time to a logic output of a first logic cell driving said one node connection;
• and
• a virtual connection for capacitive coupling for transmitting to said delay adding means a logic output of a second logic cell driving a node connection corresponding to said different wire,
• wherein the delay adding means is capable of changing the delay time to be added to a logical output of a first logic cell in accordance with the logical output of the second logic cell transmitted by the virtual connection for capacitive coupling.

A back annotation method of feedbacking a wiring delay time information after layout to logic simulation, comprising the steps of:

• providing, in a netlist used for the logic simulation, delay adding means for adding delay time to a logic output of a first logic cell driving a node connection corresponding to one wire having a coupled capacitance between a different wire and itself;
• providing, in said netlist, a virtual connection for capacitive coupling that transmits to the delay adding means a logic output of a second logic cell driving a node connection corresponding to the different wire;
• and
• using the delay adding means for changing the delay time to be added to a logical output of a first logic cell in accordance with the logical output of the second logic cell transmitted by the virtual connection for capacitive coupling.