Synchronizing signal generation circuit

A synchronizing signal generation circuit comprising:

• circuit means that separates and extracts a horizontal synchronizing signal and a vertical synchronizing signal from a signal in which the horizontal synchronizing signal and the vertical synchronizing signal are combined;
• PLL circuit means provided with a phase comparison circuit, a voltage-controlled oscillator that outputs signals of oscillation frequency that accords with an output of said phase comparison circuit, a first frequency divider that frequency divides an output of said voltage-controlled oscillator and generates clock signals, a second frequency divider that frequency divides an output of said first frequency divider, and a horizontal synchronizing signal reproduction circuit that generates a reproduced horizontal synchronizing signal from an output of said second frequency divider;
• wherein the reproduced horizontal synchronizing signal is directed to said phase comparison circuit as a signal to be compared;
• pulse signal generation circuit means, receiving said horizontal synchronizing signal output from said circuit means, to generate pulse signals that are synchronized with said horizontal synchronizing signal and are of a time constant containing a steady-state phase error of said PLL circuit that occurs during phase comparison;
• signal conversion circuit means, responsive to said pulse signals, for sampling said horizontal synchronization signal to generate a signal indicative of active interval and inactive intervals of said vertical synchronizing signal;
• phase comparison inhibiting circuit means that directs an output of said signal conversion circuit means to said phase comparison circuit and inhibits phase comparison during the active interval of said vertical synchronizing signal;
• vertical synchronizing signal reproduction circuit means that generates a reproduced vertical synchronizing signal from said vertical synchronizing signal of said circuit means and said reproduced horizontal synchronizing signal of said horizontal synchronizing signal reproduction circuit;
• and
• retiming circuit means that retimes said reproduced vertical synchronizing signal according to an output of said second frequency divider.

A synchronizing signal generation circuit comprising:

• circuit means that separates and extracts a horizontal synchronizing signal and a vertical synchronizing signal from a signal in which the horizontal synchronizing signal and the vertical synchronizing signal are combined;
• PLL circuit means provided with a phase comparison circuit, a voltage-controlled oscillator that outputs signals of oscillation frequency that accords with an output of said phase comparison circuit, and a frequency divider that frequency divides an output of said voltage-controlled oscillator and generates clock signals, wherein an output of said frequency divider is directed to said phase comparison circuit as a signal to be compared;
• pulse signal generation circuit means, receiving said horizontal synchronizing signal output from said circuit means, to generate pulse signals that are synchronized with said horizontal synchronizing signal and are of a time constant containing the steady-state phase error of said PLL circuit that occurs in phase comparison;
• signal conversion circuit means, responsive to said pulse signals, for sampling said horizontal synchronization signal to generate a signal indicative of active interval and inactive intervals of said vertical synchronizing signal;
• phase comparison inhibiting circuit means that directs an output of said signal conversion circuit means to said phase comparison circuit of said PLL circuit and inhibits phase comparison during the active interval of said vertical synchronizing signal;
• delay circuit comprising at least one basic delay element, said basic delay element including:
• at least a first and a second stage logic element connected in series and a dummy logic element connected in parallel between the first stage logic element and the second stage logic element,
• wherein said at least one basic delay element is connected in n stages (where n is a natural number), and a delay tap is extracted from an output of each basic delay element stage;
• and wherein the output of said frequency divider of said PLL circuit means is input to the delay circuit and the amount of delay of the frequency-divider output can be regulated in steps.