Back to results
US 5,686,932 AGranted
Compensative driving method type liquid crystal display device
AssigneeKabushiki Kaisha Toshiba
InventorSatoru Tomita
Life of this patent
Estimating the term…
Abstract
To compensate for voltage level shifts on the electrode of a liquid crystal display (LCD) pixel caused by parasitic capacitances between electrodes of a switching, thin film transistor (TFT) operating to apply image signal voltages to the LCD pixel electrode, a controlled voltage is applied to a storage capacitor connected in parallel with the LCD pixel to compensate for the voltage level shifts. As a result, an LCD image display, free of flicker and brightness nonuniformities, is achieved.
Claims25
A liquid crystal display device comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect with the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines, and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a storage capacitor formed between the pixel electrode and a storage capacitor line;
- a counter electrode disposed opposite to the pixel electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- and
- means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein the storage capacitor line voltage, the polarity of which is inverted with respect to a second standard potential white substantially synchronized with the polarity inversion of the image signal voltage, is applied to the storage capacitor line so as to compensate for a change of a liquid crystal applying voltage substantially synchronized with the polarity inversion of the image signal voltage in each frame period.
6 more elements
A liquid crystal display device, comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect with the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines, and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a storage capacitor formed between the pixel electrode and a storage capacitor line;
- a counter electrode disposed opposite to the pixel electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- means for supplying a storage capacitor line voltage to the storage capacitor line;
- and
- counter electrode driving means for applying a direct current voltage to the counter electrode,
- wherein the storage capacitor line voltage, the polarity of which is inverted with respect to a second standard potential while substantially synchronized with the polarity inversion of the image signal voltage, is applied to the storage capacitor line so as to compensate for a change of a liquid crystal applying voltage substantially synchronized with the polarity inversion of the image signal voltage, and
- wherein an amplitude of the storage capacitor line voltage, substantially synchronized with the image signal voltage, is in the range of .vertline.-CDS.times.dVX/Cs.vertline./5 to .vertline.-CDS.times.dVX/Cs.vertline..times.10,
- wherein CDS is a parasitic capacitance associated with a drain electrode of the transistor switching element and a source electrode of the transistor switching element, dVX is an amplitude of the image signal voltage, and Cs is a capacitance of the storage capacitor.
9 more elements
A liquid crystal display device comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect with the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines, and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a storage capacitor formed between the pixel electrode and a storage capacitor line;
- a counter electrode disposed opposite to the pixel electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- and
- means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein the storage capacitor line voltage, the polarity which is inverted with respect to a second standard potential while substantially synchronized with the polarity inversion of the image signal voltage, is applied to the storage capacitor line so as to compensate for a change of a liquid crystal applying voltage substantially synchronized with the polarity inversion of the image signal voltage, and
- wherein the amplitude of the storage capacitor line voltage is in the range of .vertline.{(CGS+CDS+Cs)dVc-CDS.times.dvX}/Cs.vertline./5 to .vertline.{(CGS+CDS+Cs)dVc-CDS.times.dVX}/Cs.vertline..times.10,
- wherein CGS is a parasitic capacitance associated with a gate electrode and a source electrode of the transistor switching element, CDS is a parasitic capacitance associated with a drain electrode and the source electrode of the transistor switching element, dVc is an amplitude of the counter electrode voltage applied to the counter electrode, dVX is an amplitude of the image signal voltage, and Cs is a capacitance of the storage capacitor.
8 more elements
A liquid crystal display device comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect with the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines, and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a counter electrode disposed opposite to the pixel electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- a storage capacitor formed between the pixel electrode and a storage capacitor line disposed substantially in parallel with the scanning line;
- and
- storage capacitor line driving means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein a potential level of the storage capacitor line voltage is changed substantially synchronizing with the scanning pulse, a direction of the potential level change of the storage capacitor line voltage is opposite to a direction of a potential level change of the scanning pulse, so as to compensate for a change of liquid crystal applying voltage substantially synchronizing with the scanning pulse.
6 more elements
A liquid crystal display device comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect with the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a counter electrode disposed opposite to the pixel electrode, wherein a direct current voltage is applied to the counter electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- a storage capacitor formed between the pixel electrode and a storage capacitor line;
- and
- storage capacitor line voltage driving means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein the polarity of the storage capacitor line voltage is inverted with respect to a second standard potential while synchronized with the polarity inversion of the image signal voltage so as to compensate for a first change of a liquid crystal applying voltage substantially synchronized with the polarity inversion of the image signal voltage in each frame period, and wherein the potential of the storage capacitor line voltage changes while substantially synchronized with the scanning pulse so as to compensate for a second change of a liquid crystal applying voltage substantially synchronized with the scanning pulse in each frame period.
6 more elements
A liquid crystal display device, comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect with the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a counter electrode disposed opposite to the pixel electrode, wherein a direct current voltage is applied to the counter electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- a storage capacitor formed between the pixel electrode and a storage capacitor line;
- and
- storage capacitor line voltage driving means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein the polarity of the storage capacitor line voltage is inverted with respect to a second standard potential while synchronized with the polarity inversion of the image signal voltage so as to compensate for a first change of a liquid crystal applying voltage substantially synchronized with the polarity inversion of the image signal voltage, and wherein the potential of the storage capacitor line voltage changes while substantially synchronized with the scanning pulse so as to compensate for a second change of a liquid crystal applying voltage substantially synchronized with the scanning pulse, and
- wherein a change of the storage capacitor line voltage, substantially synchronized with the scanning pulse, is in the range of .vertline.(-CGS.times.dVY)/Cs.vertline./2 to .vertline.(-CGS.times.dVY)/Cs.vertline..times.2,
- wherein CGS is a parasitic capacitance associated with a gate electrode and a source electrode of the transistor switching element, dVY is an amplitude of the scanning pulse and Cs is a capacitance of the storage capacitor.
8 more elements
A liquid crystal display device comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect with the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a counter electrode disposed opposite to the pixel electrode, wherein a direct current voltage is applied to the counter electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- a storage capacitor formed between the pixel electrode and a storage capacitor line;
- and
- storage capacitor line voltage driving means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein the polarity of the storage capacitor line voltage is inverted with respect to a second standard potential while synchronized with the polarity inversion of the image signal voltage so as to compensate for a first change of a liquid crystal applying voltage substantially synchronized with the polarity inversion of the image signal voltage, and wherein the potential of the storage capacitor line voltage changes while substantially synchronized with the scanning pulse so as to compensate for a second change of a liquid crystal applying voltage substantially synchronized with the scanning pulse, and
- wherein the change of the storage capacitor line voltage, substantially synchronizing with the image signal voltage, is in the range of .vertline.-CDS{VX(TF1)-VX(TF2)}/Cs.vertline./5 to .vertline.-CDS{VX(TF1)-VX(TF2)}/Cs.vertline..times.5
- wherein CDS is a parasitic capacitance associated with a drain electrode and a source electrode of the transistor switching element, VX(TF1) is an image signal voltage for one period (TF1), VX(TF2) is an image signal voltage for a next period (TF2) and Cs is a capacitance of the storage capacitor.
8 more elements
A liquid crystal display device comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a counter electrode disposed opposite to the pixel electrode, wherein a counter electrode voltage, having a counter voltage polarity inverted with respect to a second standard potential while synchronized with the image signal voltage, is applied to the counter electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- a storage capacitor line and a storage capacitor formed between the pixel electrode and the storage capacitor line disposed in parallel with the scanning lines;
- and
- storage capacitor voltage driving means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein the polarity of the storage capacitor line voltage is inverted with respect to a third standard potential in the same direction as the polarity of the counter electrode voltage while synchronizing with the counter electrode voltage, so as to compensate for a first change of a liquid crystal applying voltage substantially synchronized with the image signal voltage, and wherein the potential of the storage capacitor line voltage changes while substantially synchronized with the scanning pulse so as to compensate for a second change of a liquid crystal applying voltage substantially synchronized with the scanning pulse in each frame period.
6 more elements
A liquid crystal display device, comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a counter electrode disposed opposite to the pixel electrode, wherein a counter electrode voltage, having a counter voltage polarity inverted with respect to a second standard potential while synchronized with the image signal voltage, is applied to the counter electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- a storage capacitor line and a storage capacitor formed between the pixel electrode and the storage capacitor line disposed in parallel with the scanning lines;
- and
- storage capacitor voltage driving means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein the polarity of the storage capacitor line voltage is inverted with respect to a third standard potential in the same direction as the polarity of the counter electrode voltage while synchronizing with the counter electrode voltage, so as to compensate for a first change of a liquid crystal applying voltage substantially synchronized with the image signal voltage, and wherein the potential of the storage capacitor line voltage changes while substantially synchronized with the scanning pulse so as to compensate for a second change of a liquid crystal applying voltage substantially synchronized with the scanning pulse, and
- wherein a change of the storage capacitor line voltage, substantially synchronizing with the scanning pulse, is in the range of .vertline.(-CGS.times.dVY)/Cs.vertline./2 to .vertline.(-CGS.times.dVY)/Cs.vertline..times.2,
- wherein CGS is a parasitic capacitance associated with a gate electrode and a source electrode of the transistor switching element, dVY is an amplitude of the scanning pulse and Cs is a capacitance of the storage capacitor.
8 more elements
A liquid crystal display device, comprising:
- matrix wiring having a plurality of scanning lines and a plurality of signal lines disposed to intersect the plurality of scanning lines, wherein a scanning pulse is applied to the scanning lines and an image signal voltage, having a polarity periodically inverted with respect to a first standard potential, is applied to the signal lines;
- a pixel electrode disposed at each intersection of the plurality of scanning lines and the plurality of signal lines;
- a transistor switching element included at each intersection of the plurality of scanning lines and the plurality of signal lines and connected to each pixel electrode;
- a counter electrode disposed opposite to the pixel electrode, wherein a counter electrode voltage, having a counter voltage polarity inverted with respect to a second standard potential while synchronized with the image signal voltage, is applied to the counter electrode;
- a liquid crystal composition held between the pixel electrode and the counter electrode;
- a storage capacitor line and a storage capacitor formed between the pixel electrode and the storage capacitor line disposed in parallel with the scanning lines;
- and
- storage capacitor voltage driving means for supplying a storage capacitor line voltage to the storage capacitor line,
- wherein the polarity of the storage capacitor line voltage is inverted with respect to a third standard potential in the same direction as the polarity of the counter electrode voltage while synchronizing with the counter electrode voltage, so as to compensate for a first change of a liquid crystal applying voltage substantially synchronized with the image signal voltage, and wherein the potential of the storage capacitor line voltage changes while substantially synchronized with the scanning pulse so as to compensate for a second change of a liquid crystal applying voltage substantially synchronized with the scanning pulse, and
- wherein a change of the storage capacitor line voltage, substantially synchronized with the polarity inversion of the image signal voltage, is in the range of .vertline.(CGS+CDS+Cs){VX(TF1)-VX(TF2)}-CDS{VX(TF1)-VX(TF2)}/Cs.vertline./ 5 to .vertline.(CGS+CDS+Cs){VC(TF1)-VC(TF2)}-CDS{VX(TF1)-VX(TF2)}/Cs.vertline.. times.10,
- wherein CGS is a parasitic capacitance associated with a gate electrode and a source electrode of the transistor switching element, CDS is a parasitic capacitance associated with a drain electrode and a source electrode of the transistor switching element, Cs is a capacitance of the storage capacitor, VC(TF1) is a counter electrode voltage for one period (TF1), VC(TF2) is a counter electrode voltage for a next period (TF2), VX(TF1) is an image signal voltage for one period (TF1), and VX(TF2) is an image signal voltage for a next period (TF2).
8 more elements
Dependencies are inferred from the claim text.