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US 5,686,851 AGranted
Variable delay circuit
AssigneeOki Electric Industry Co., Ltd.
InventorsHiroyuki Yamada, Shouhei Seki
Life of this patent
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AssigneeOki Electric Industry Co., Ltd.
InventorsHiroyuki Yamada, Shouhei Seki
Estimating the term…
A variable delay circuit capable of changing delay time includes a latch circuit constituted of a pair of inverters cross-coupled to each other and a transistor serving for reducing voltage difference between two inputs of the latch circuit based on a control signal given thereto. The control signal is also supplied to a pair of transfer gates to control the delay time of the variable delay circuit. The latch circuit has two inputs, between which the transistor is coupled, coupled to the respective transfer gates' ends, at which buffers are respectively coupled to feed output signals. When the control signal reaches a high level, the state of the transistor becomes one of low impedance, so that the voltage difference between the two inputs of the latch circuit is reduced, and so that the state of the latch circuit can be quickly and easily changed with little energy. The variable delay circuit can set the minimum delay time smaller than that of the conventional circuit, which allows the variable range of delay time to be wider.
A variable delay circuit for delaying, based on a control signal, a pair of input signals whose states constitute logical complements of one another, comprising:
A variable delay circuit for delaying, based on a control signal, a pair of input signals whose states constitute logical complements of one another, comprising:
Dependencies are inferred from the claim text.