Power-up/power-down reset circuit for low voltage interval
AssigneeMosaid Technologies Incorporated
InventorsIan Mes, Graham Allan
Life of this patent
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Abstract
A power up, power down reset circuit formed of charge storage apparatus for receiving and storing charge from one pole of a voltage supply, a pair of complementary field effect transistors having source-drain circuits connected in series aiding direction between the charge storage apparatus and another pole of the voltage supply, apparatus for connecting the one pole of the voltage supply to a gate of one transistor of the pair of transistors, apparatus for applying a voltage derived from the one pole of the voltage supply but having a value reduced from voltage of the voltage supply, to a gate of another transistor of the pair of transistors, and apparatus for providing a reset pulse from a junction between the source-drain circuits of the pair of transistors.
Claims9
A power up, power down reset circuit comprising:
- (a) charge storage means for receiving and storing charge from one pole of a voltage supply,
- (b) a pair of complementary field effect transistors having source-drain circuits connected in series aiding direction between the charge storage means and another pole of the voltage supply,
- (c) means for connecting said one pole of the voltage supply directly to a gate of one transistor of said pair of transistors,
- (d) means for applying a voltage derived from said one pole of the voltage supply but having a value reduced from the voltage of the voltage supply, to a gate of the other transistor of said pair of transistors, and
- (e) means for providing a reset pulse from a junction between the source-drain circuits of said pair of transistors.
Dependencies are inferred from the claim text.