Integrated circuit pins configurable as a clock input pin and as a digital I/O pin or as a device reset pin and as a digital I/O pin and method therefor
AssigneeMicrochip Technology Incorporated
InventorsRichard L. Hull, Ryan Scott Ellison
Life of this patent
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Abstract
The present invention relates to a configurable IC device pin. The IC device pin may be a device clock input pin or a digital I/O pin in one embodiment of the present invention, or a reset pin or a digital I/O pin in another embodiment of the present invention. Both embodiments of the present invention use a memory device to store information to configure the IC device pin. Input/Output logic is also used in both embodiments in order to transfer data to and from the IC device pin when the IC device pin is configured as a digital I/O pin.
Claims24
A system for configuring an integrated circuit (IC) device pin as a clock input pin and as a digital input/output (I/O) pin comprising, in combination:
- an IC device pin;
- memory means for storing a value to configure said IC device pin as said clock input pin and for storing a value to configure said IC device pin as said digital I/O pin;
- I/O logic means coupled to an output of said memory means for writing data out of said IC device pin and for reading data in from said IC device pin when said IC device pin is configured as said digital I/O pin;
- and
- clock logic gate means coupled to said output of said memory means and to said IC device pin for outputting a clock signal to an IC device coupled to said IC device pin when said IC device pin is configured as said clock input pin.
The system in accordance with claim 8 wherein said output driver circuit means comprises:
- a PMOS transistor having a gate coupled to an output of said OR gate;
- and
- an NMOS transistor having a gate coupled to an output of said AND gate.
A system for configuring an IC device pin as a device reset pin and as a digital I/O pin comprising, in combination:
- an IC device pin;
- memory means for storing a value to configure said IC device pin as said device reset pin and for storing a value to configure said IC device pin as said digital I/O pin;
- I/O logic means coupled to an output of said memory means for writing data out of said IC device pin and for reading data in from said IC device pin when said IC device pin is configured as said digital I/O pin;
- and
- device reset logic gate means coupled to said output of said memory means and to said IC device pin for outputting a reset signal when said IC device pin is configured as said device reset pin.
A method of providing a system for configuring an IC device pin as a clock input pin and as a digital I/O pin comprising the steps of:
- providing an IC device pin;
- providing memory means for storing a value to configure said IC device pin as said clock input pin and for storing a value to configure said IC device pin as said digital I/O pin;
- providing I/O logic means coupled to an input of said memory means for writing data out of said IC device pin and for reading data in from said IC device pin when said IC device pin is configured as said digital I/O pin;
- providing clock logic gate means coupled to said output of said memory means and to said IC device pin for outputting a clock signal when said IC device pin is configured as said clock input pin;
- and
- providing bus means coupled to said I/O logic means for transferring data to and from said I/O logic means when said IC device pin is configured as said digital I/O pin.
A method of providing a system for configuring an IC device pin as a device reset pin and as a digital I/O pin comprising the steps of:
- providing an IC device pin;
- providing memory means for storing a value to configure said IC device pin as said device reset pin and for storing a value to configure said IC device pin as said digital I/O pin;
- providing I/O logic means coupled to an output of said memory means for writing data out of said IC device pin and for reading data in from said IC device pin when said IC device pin is configured as said digital I/O pin;
- providing device reset logic gate means coupled to said output of said memory means and to said IC device pin for outputting a reset signal when said IC device pin is configured as said device reset pin;
- and
- providing bus means coupled to said I/O logic means for transferring data to and from said I/O logic means when said IC device pin is configured as said digital I/O pin.
Dependencies are inferred from the claim text.