Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology

A multilayer interconnect structure formed in an interlayer dielectric supported over a semiconductor substrate comprising:

• (a) at least one Ti/TiN landing pad comprising a layer of Ti and a first layer of TiN having a first thickness, each of said Ti/TiN landing pads formed on a conductive region surrounded by insulating regions supported over said semiconductor substrate;
• (b) said interlayer dielectric formed over said semiconductor substrate on regions including, but not limited to, said Ti/TiN landing pads and said insulating regions;
• (c) contact/via openings etched in said interlayer dielectric down to said Ti/TiN landing pads, each of said contact/via openings having a bottom and sidewalls;
• (d) a second layer of TiN having a second thickness deposited on said bottom and on said sidewalls of said contact/via openings, said second layer of TiN serving as an adhesion layer, said second thickness being less than said first thickness;
• and
• (e) a metal plug in each said contact/via openings and adhered to said bottom and sidewalls thereof by said second layer of TiN.