Compound semiconductor device on silicon substrate and method of manufacturing the same
AssigneeFujitsu Limited
InventorsTatsuya Ohori, Kanae Fukuzawa
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Abstract
E and D mode HEMTs are integrated in a laminated layer of pairs of GaAs/AlGaAs layers formed on the same GaAs-on-Si substrate. The gate electrodes of E and D mode HEMTs are formed on different GaAs layers. The GaAs layer on Si contains crystal defects. It is hypothesized that the defects extend upward in the laminated layer of pairs of GaAs/AlGaAs layers formed on the GaAs layer with such crystal defects. Etch pits are generated as the AlGaAs layer is etched by ammonium etchant. Generation of etch pits can be suppressed by etching the whole part of the exposed AlGaAs layer and exposing the GaAs layer under the gate electrode.
Claims20
A compound semiconductor device on a silicon substrate having at least two transistors with different threshold values, comprising:
- a silicon substrate;
- a compound semiconductor laminated structure epitaxially grown on said silicon substrate, said laminated structure including first and second laminates with the second laminate being disposed on the first laminate, each laminate comprising first and second compound semiconductor layers, said first compound semiconductor layer having a wider band gap energy than that of said second compound semiconductor layer, the second compound semiconductor layer of said first laminate being substantially undoped;
- and
- two gate electrodes formed respectively on exposed portions of said second compound semiconductor layers of said first and second laminates.
A compound semiconductor device on a silicon substrate having at least two transistors with different threshold values, comprising:
- a silicon substrate;
- a compound semiconductor laminated structure epitaxially grown on said silicon substrate, the laminated structure having crystal defects which extend from an interface between the silicon substrate and the laminated structure and through the laminated structure, said laminated structure including first and second laminates with the second laminate being disposed on the first laminate, each laminate comprising first and second compound semiconductor layers, said first compound semiconductor layer having a wider band gap energy than that of said second compound semiconductor layer, the first compound semiconductor layers of the first and second laminates having the crystal defects therein with the crystal defects in the first compound semiconductor layer of the first laminate, but not the second laminate, being subjected to reactive ion etching and then ammonia etching during fabrication;
- an E-mode gate electrode formed on an exposed portion of the second compound semiconductor layer of the first laminate;
- and
- a D-mode gate electrode formed on an exposed portion of said second compound semiconductor layer of said second laminate.
Dependencies are inferred from the claim text.