Process for forming field isolation structure with minimized encroachment effect
AssigneeUnited Microelectronics Corp.
InventorFang-Ching Chao
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AssigneeUnited Microelectronics Corp.
InventorFang-Ching Chao
Estimating the term…
A method for minimizing the impurity encroachment effect of the field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a first layer and a second layer are deposited on a laminate comprising a substrate having thereon the stacked layers. A photo-resist mask which defines the isolation regions is then formed and the unmasked portion is removed. A third layer is deposited and then is etched anisotropically to form the spacers. A fourth layer is deposited and the chemical-mechanical polishing (CMP) method is applied until the first layer is exposed. After the first layer is removed, the channel-stop ions are implanted, and the spacers are removed for forming the isolation regions by the oxidation. As a result, the channel stop region is self-aligned to the resulting field oxide and the isolation structure is free of the impurity encroachment effect.
A process for forming isolation regions on a semiconductor substrate, the process comprising:
A process for forming isolation regions on a semiconductor substrate, the process comprising:
A process for forming isolation regions on a semiconductor substrate, the process comprising:
Dependencies are inferred from the claim text.