Process for fabricating high-resistance load resistors using dummy polysilicon in four-transistor SRAM devices

Abstract

A process for fabricating load resistors for memory cell units of a semiconductor SRAM device. The process includes providing a silicon substrate containing an intermediate semiconductor device having a gate structure and source/drain regions for a transistor of the cell unit. A first dielectric layer is then formed over the surface of the silicon substrate, wherein the first dielectric layer has an opening via exposing the gate electrode of the gate structure. A polysilicon layer is then deposited and patterned for forming a first connector in the via, at least one dummy structure on the first dielectric layer, and a second connector. A second dielectric layer is then formed to have two further vias respectively exposing the first and second connectors. A polysilicon load resistor is formed and coupled electrically to the first and second connectors and extends over the surface of the at least one dummy structure so as to have an elongated length.

Dependencies are inferred from the claim text.