US 5,686,324 AGranted

Process for forming LDD CMOS using large-tilt-angle ion implantation

AssigneeMosel Vitelic, Inc.

InventorsChih-Hsien Wang, Min-Liang Chen

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Abstract

A method and resulting integrated circuit device, and in particular a CMOS integrated circuit device, having a fabrication method and structure therefor for an improved lightly doped drain region. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectic over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 45.degree. or greater from a perpendicular to the gate electrodes in both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well region. Sidewall spacers are then formed on edges of the gate electrodes. The method then performs two separate N type implants into the P type well region, each at different angles and dosages to form the N type LDD source/drain region for an NMOS device. The method also performs two separate P type implants into the N type well region, each at different angles and dosages to form the P type LDD source/drain region for a PMOS device. The present LDD fabrication method provides a relatively consistent and easy to fabricate CMOS LDD region, with less masking steps and improved device performance.

Claims11

Dependent claims

A method of fabricating a CMOS integrated circuit device, said method comprising:

providing a semiconductor substrate, said semiconductor substrate comprising a first well region of a first conductivity type and a second well region of a second conductivity type, said first well region having a first gate electrode overlying a first gate dielectric layer, said second well region having a second gate electrode overlying a second gate dielectric layer;
blanketly introducing a first impurity of said second conductivity type into said first well region and said second well region, said first impurity in said first well region defining a first LDD region;
forming first sidewall spacers on edges of said first gate electrode and second sidewall spacers on edges of said second gate electrode;
introducing a second impurity of said second conductivity type into said first well region and introducing a third impurity of said second conductivity type into said first well region said second impurity in said first well region defining a first dose of a first source/drain region, said third impurity in said first well region defining a second dose of said first source/drain region;
and
introducing a fourth impurity of said first conductivity type into said second well region and introducing a fifth impurity of said first conductivity type into said second well region, said fourth impurity in said second well region defining a second LDD region, said fifth impurity in said second well region defining a second source/drain region.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/625,587Filed 28 Mar 1996
Granted: 11 Nov 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/605
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having significant overlap between the lightly-doped extensions…
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe