US 5,684,980 A · FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions

Abstract

An array of FPGAs change their configurations successively during performance of successive user-defined algorithms. Adjacent FPGAs are connected through external field programmable interconnection devices (FPINs) or cross-bar switches. The array includes a processor-like device capable of performing the computations necessary to reconfigure the FPGAs in the array in accordance with the next algorithm to be performed. Preferably, this processor-like device is itself a "control" array of interconnected FPGAs which have been configured to emulate a selected microprocessor architecture which accepts user-defined primitives corresponding to an algorithm to be performed or a logic architecture to be emulated and reconfigure the FPGAs and the FPINs accordingly.

Claims36

Dependent claims

A computer, comprising:

a plurality of field programmable gate arrays (FPGAs);
a plurality of control field programmable gate arrays (control FPGAs), comprising:
(a) a first group of gates comprising means for generating from each one of a succession of computing operations, corresponding to a succession of instructions defining a program to be executed, a plurality of logic configurations defining (a) an internal logic structure of a corresponding one of said FPGAs and (b) external connections between said corresponding FPGA and others of said FPGAs, whereby to generate a succession of logic configurations for each one of said FPGAs corresponding to said succession of predetermined computing operations;
and
(b) a second group of gates comprising means for configuring each one of said FPGAs in accordance with a corresponding succession of logic configurations, whereby said plurality of FPGAs is successively reconfigured to perform said succession of predetermined computing operations sequentially so as to execute said sequence of instructions.

2 more elements

A method of operating an array of plural field programmable gates (FPGs) and a controller in order to execute a program defined by a sequence of instructions, comprising:

said controller fetching information defining a succession of computing operations, each of said computing operations corresponding to a respective group of at least a respective one of said sequence of instructions;
said controller generating from said succession of computing operations a corresponding succession of sets of respective plural logic configurations for reinactive ones of said plural FPGs, each of said logic configurations within a set defining (a) an internal logic structure of a corresponding one of said FPGs and (b) external connections between said corresponding FPG and others of said FPGs, whereby to generate a succession of logic configurations for each one of said FPGs corresponding to said succession of computing operations;
said controller configuring each one of said array of FPGs in accordance with a corresponding succession of logic configurations, wherein said array of FPGs is successively reconfigured to perform said succession of computing operations sequentially so as to execute said sequence of instructions of said program.

A computer, comprising:

a plurality of field programmable gates (FPGs);
a plurality of control field programmable gates (control FPGs), comprising:
(a) a first group of gates comprising means for generating from each one of a succession of predetermined computing operations a plurality of logic configurations corresponding to said plurality of FPGs, each of said logic configurations defining (a) an internal logic structure of a corresponding one of said FPGs and (b) external connections between said corresponding FPG and others of said FPGs, whereby to generate a succession of logic configurations for each one of said FPGs corresponding to said succession of predetermined computing operations;
and
(b) a second group of gates comprising means for configuring each one of said FPGs in accordance with a corresponding succession of logic configurations, whereby said plurality of FPGs is successively reconfigured to perform said succession of predetermined computing operations sequentially.

2 more elements

A method of operating an array of field programmable gates (FPGs) connected to an array of control field programmable gates, comprising:

said array of control FPGs fetching information defining a succession of predetermined computing operations;
generating in said control FPGs from each one of said succession of predetermined computing operations a plurality of logic configurations corresponding to said array of FPGs, each of said logic configurations defining (a) an internal logic structure of a corresponding one of said FPGs and (b) external connections between said corresponding FPG and others of said FPGs, whereby to generate a succession of logic configurations for each one of said FPGs corresponding to said succession of predetermined computing operations;
said array of control FPGs configuring each one of said array of FPGs in accordance with a corresponding succession of logic configurations, wherein said array of FPGs is successively reconfigured to perform said succession of predetermined computing operations sequentially.

Dependencies are inferred from the claim text.

FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions

Life of this patent

FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions

Life of this patent

Abstract

Claims36