Erasable and programmable single chip clock generator
AssigneeCypress Semiconductor Corporation
InventorsEric N. Mann, John Q. Torode
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Abstract
A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.
Claims18
A circuit for generating a clock frequency comprising:
- a configuration table having a set of outputs for storing a set of configuration information to determine said clock frequency;
- an erasable and programmable non-volatile memory for storing said configuration table;
- and
- a clock generator having a set of inputs coupled to said set of outputs of said configuration table, said clock generator for generating said clock frequency,
- wherein said configuration table, said non-volatile memory and said clock generator are provided on a single chip.
A single chip circuit for generating a set of clock frequencies comprising:
- a configuration table having a set of outputs for storing a set of configuration information to determine the frequencies at which a set of clock outputs oscillate;
- an erasable and programmable non-volatile memory for storing said configuration table;
- an internal or external reference frequency source that generates a reference output;
- a first clock generator having a set of inputs coupled to said set of outputs of said configuration table and a reference input coupled to said reference output, said clock generator for generating one of said set of clock outputs at one of said frequencies determined by said configuration table;
- a plurality of fixed frequency clock generators each having a set of inputs coupled to said configuration table and a reference input coupled to said reference output, each of said plurality of clock generators having an output signal that oscillates at a fixed frequency;
- and
- a multiplexer having (i) a plurality of inputs connected to each of the outputs from said first clock generator and said plurality of clock generators and (ii) a bus input connected to one of said set of outputs of said configuration table, said multiplexer for presenting at least one of said clock output signals.
Dependencies are inferred from the claim text.