Variable delay circuit

A variable delay circuit comprising:

• a first power source line which supplies a first power source voltage;
• a second power source line which supplies a second power source voltage that is lower than the first power source voltage;
• an input terminal which receives an input signal;
• selection terminal means for receiving a selection signal, the selection terminal means comprising N selection terminals which receive N selection signals, where the N selection signals respectively correspond on a one-to-one basis with the N selection terminals and N is an integer greater than or equal to two;
• an output terminal;
• a pull-up circuit which is coupled between the first power source line and the output terminal and performs a pull-up operation based on the input signal received by the input terminal, the pull-up circuit comprising a p-channel transistor coupled in series between the first power source line and the output terminal and having a gate coupled to the input terminal;
• and
• a pull-down circuit which is coupled between the output terminal and the second power source line and performs a pull-down operation based on the input signal received by the input terminal, the pull-down circuit having a variable threshold voltage and a delay time which is selectively variable by changing the threshold voltage in response to the selection signal received by the selection terminal means, to thereby provide an output signal at the output terminal which is delayed relative to the input signal, the pull-down circuit comprising
• N series circuits coupled in parallel between the output terminal and the second power source line,
• each of the N series circuits including n-channel transistors connected in series in M stages which extend between the output terminal and the second power source line, where M is an integer greater than or equal to two, each of the n-channel transistors having a respective gate,
• in each of the N series circuits, one of the n-channel transistors having a gate coupled to the input terminal and each of remaining n-channel transistors within the series circuit having a gate coupled in common with the gates of the other remaining n-channel transistors within the series circuit to a corresponding one of the N selection terminals, and
• one of the N series circuits being selected in response to the N selection signals to thereby determine the delay time of the pull-down circuit.

A variable delay circuit comprising:

• a first power source line which supplies a first power source voltage;
• a second power source line which supplies a second power source voltage that is lower than the first power source voltage;
• an input terminal which receives an input signal;
• selection terminals means for receiving a selection signal;
• an output terminal for outputting an output signal which is delayed relative to the input signal;
• a pull-up circuit which is coupled between the first power source line and the output terminal and performs a pull-up operation based on the input signal received by the input terminal, the pull-up circuit comprising
• N series circuits coupled in parallel between the first power source line and the output terminal, where N is an integer greater than or equal to two,
• each of the N series circuits including p-channel transistors connected in series in M stages extending between the first power source line and the output terminal, where M is an integer greater than or equal to two,
• in each of the N series circuits, one of the p-channel transistors having a gate coupled to the input terminal and each of the remaining p-channel transistors within the series circuit having a gate coupled to the selection terminal means,
• one of the N series circuits being selected in response to the selection signal to thereby determine the delay time of the pull-up circuit;
• and
• a pull-down circuit which is coupled between the output terminal and the second power source line and performs a pull-down operation based on the input signal received by the input terminal, the pull-down circuit comprising an n-channel transistor coupled in series between the output terminal and the second power source line and having a gate coupled to the input terminal;
• wherein the pull-up circuit has a variable threshold voltage and a delay time which is selectively variable by changing the threshold voltage in response to the selection signal received by the selection terminal means, to thereby provide an output signal at the output terminal which is delayed relative to the input signal.

A variable delay circuit comprising:

• a first power source line which supplies a first power source voltage;
• a second power source line which supplies a second power source voltage that is lower than the first power source voltage;
• an input terminal which receives an input signal;
• selection terminals means for receiving a selection signal, the selection terminals means comprising N selection terminals which receive N selection signals, where the N selection signals respectively correspond on a one-to-one basis with the N selection terminals and N is an integer greater than or equal to two;
• an output terminal for outputting an output signal which is delayed relative to the input signal;
• a pull-up circuit which is coupled between the first power source line and the output terminal and performs a pull-up operation based on the input signal received by the input terminal, the pull-up circuit comprising
• N series circuits coupled in parallel between the first power source line and the output terminal,
• each of the N series circuits including p-channel transistors connected in series in M stages extending between the first power source line and the output terminal, where M is an integer greater than or equal to two, each of the p-channel transistors having a respective gate,
• in each of the N series circuits, one of the p-channel transistors having a gate coupled to the input terminal and each of the remaining p-channel transistors within the series circuit having a gate coupled in common with the gates of the other remaining p-channel transistors within the series circuit to a corresponding one of the N selection terminals,
• one of the N series circuits being selected in response to the N selection signals to thereby determine the delay time of the pull-up circuit;
• and
• a pull-down circuit which is coupled between the output terminal and the second power source line and performs a pull-down operation based on the input signal received by the input terminal, the pull-down circuit comprising an n-channel transistor coupled in series between the output terminal and the second power source line and having a gate coupled to the input terminal;
• wherein the pull-up circuit has a variable threshold voltage and a delay time which is selectively variable by changing the threshold voltage in response to the selection signal received by the selection terminal means, to thereby provide an output signal at the output terminal which is delayed relative to the input signal.