US 5,684,422 A · Pipelined microprocessor including a high speed single-clock latch circuit

Abstract

A pipelined microprocessor is provided including a latch circuit wherein a first transmission gate is electrically coupled in series with a second transmission gate between an output line of a first pipeline stage and an input stage of a subsequent pipeline stage. The latch circuit is controlled by a single clock signal wherein a delay element is employed to simultaneously enable both transmission gates upon an edge of the clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input line is electrically coupled to the output line. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input line is decoupled from the output line. In one implementation, the delay element is implemented with a set of serially coupled inverters, and the length of the time delay controls the time window during which both transmission gates are enabled.

Claims22

Dependent claims

A pipelined microprocessor comprising:

a first combinational logic circuit forming a first pipeline stage within said microprocessor;
a second combinational logic circuit forming a subsequent pipeline stage within said microprocessor;
and
a latch circuit coupled between an output line of said first combinational logic circuit and an input line of said second combinational logic circuit, said latch circuit including:
a plurality of transmission gates serially coupled between said first combinational logic circuit and said second combinational logic circuit, wherein a first of said plurality of transmission gates is controlled by a clock signal;
a keeper circuit coupled to said first of said plurality of transmission gates, wherein said keeper circuit is configured to maintain a logic value at an output terminal of said first of said plurality of transmission gates;
and
a delay element coupled to a second of said plurality of transmission gates, wherein said second of said plurality of transmission gates is controlled by a delayed version of said clock signal, whereby an edge of said clock signal results in said first and said second of gate plurality of transmission gates being enabled concurrently for a predetermined period and wherein a node between said first transmission gate and said second transmission gate is floated when said second transmission gate is not enabled.

5 more elements

A pipelined microprocessor comprising:

a first combinational logic circuit forming a first pipeline stage within said microprocessor;
a second combinational logic circuit forming a subsequent pipeline stage within said microprocessor;
and
a latch circuit coupled between an output line of said first combinational logic circuit and an input line of said second combinational logic circuit, said latch circuit including:
a data input node for receiving an input signal;
a first transmission gate having a first terminal coupled to said data input node, a second terminal, and a control terminal;
a second transmission gate having a first terminal coupled to said second terminal of said first transmission gate, a second terminal, and a control terminal coupled to receive a clock signal;
a keeper circuit coupled to said second terminal of said second transmission gate, wherein said keeper circuit is configured to maintain a logic value at said second terminal of said second transmission gate;
and
a delay element coupled to said control terminal of said first transmission gate, wherein said delay element is capable of delaying said clock signal to thereby provide a delayed clock signal to said control terminal of said first transmission gate, whereby an edge of said clock signal results in said first transmission gate and said second transmission gate being enabled concurrently for a predetermined period and wherein a node between said first transmission gate and said second transmission gate is floated when said first transmission gate is not enabled.

7 more elements

A pipelined microprocessor, comprising:

a first combinational logic circuit forming a first pipeline stage within said microprocessor;
a second combinational logic circuit forming a subsequent pipeline stage within said microprocessor;
and
a latch circuit coupled between an output line of said first combinational logic circuit and an input line of said second combinational logic circuit, said latch circuit including:
a data input node for receiving an input signal;
a first transmission gate having a first terminal coupled to said data input node, a second terminal, and a control terminal such that said input signal is transmitted from said first terminal of said first transmission gate to said second terminal of said first transmission gate when said first transmission gate is enabled;
a second transmission gate having a first terminal, a second terminal, and a control terminal, wherein said first terminal of said second transmission gate is coupled to the second terminal of said first transmission gate, and wherein said control terminal of said second transmission gate is coupled to receive a clock signal;
a keeper circuit coupled to the second terminal of the second transmission gate, wherein said keeper circuit is configured to maintain a logic value at said second terminal of said second transmission gate;
and
a delay element coupled to said control terminal of said first transmission gate, wherein said delay element is configured to delay said clock signal to thereby provide a delayed clock signal to said control terminal of said first transmission gate, whereby an edge of said clock signal results in said first transmission gate and said second transmission gate being enabled concurrently for a predetermined period;
and wherein a logic value reflecting a value of said input signal is established at said first terminal of said second transmission gate and said second terminal of said second transmission gate only during said predetermined period of time when said first transmission gate and said second transmission gate are concurrently enabled and wherein a node between said first transmission gate and said second transmission gate is floated when said first transmission gate is not enabled.

8 more elements

A pipelined microprocessor comprising:

a first combinational logic circuit forming a first pipeline stage within said microprocessor;
a second combinational logic circuit forming a subsequent pipeline stage within said microprocessor;
and
a latch circuit coupled between an output line of said first combinational logic circuit and an input line of said second combinational logic circuit, said latch circuit including:
a data input node for receiving an input signal;
a first transmission gate having a first terminal coupled to said data input node, a second terminal, and a control terminal, wherein said first transmission gate is configured such that said input signal is transmitted from said first terminal of said first transmission gate to said second terminal of said first transmission gate when said first transmission gate is enabled;
a second transmission gate having a first terminal, a second terminal, and a control terminal, wherein said first terminal of said second transmission gate is coupled to the second terminal of said first transmission gate, and wherein said control terminal of said second transmission gate is coupled to receive a clock signal;
a keeper circuit coupled to the second terminal of the second transmission gate, wherein said keeper circuit is configured to maintain a logic value at said second terminal of said second transmission gate;
and
a delay element coupled to said control terminal of said first transmission gate, wherein said delay element is configured to delay said clock signal to thereby provide a delayed clock signal to said control terminal of said first transmission gate, whereby an edge of said clock signal results in said first transmission gate and said second transmission gate being enabled concurrently for a predetermined period;
and wherein a node between said first transmission gate and said second transmission gate is floated when said first transmission gate is not enabled.

8 more elements

Dependencies are inferred from the claim text.

Pipelined microprocessor including a high speed single-clock latch circuit

Life of this patent

Pipelined microprocessor including a high speed single-clock latch circuit

Life of this patent

Abstract

Claims22