Condensed single block PLA plus PAL architecture
AssigneePhilips Electronics North America Corporation
InventorsSchuyler E. Shimanek, Thomas J. Davies
Life of this patent
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Abstract
A condensed single block PAL plus PLA architecture utilizing a rectangular shape is shown. By interleaving the ORterms of the PLA array with the Pterms of the PAL array, a significant amount of die space is saved when incorporating the circuit with silicon. The decode routing required is now simplified and the propagation delay skews through the array are also reduced.
Claims5
A condensed single block PLA plus PAL architecture comprising:
- at least one PLA array having a plurality of Pterm elements each having an input and an output, and a plurality of AND gates each having and output, and an input coupled to one of said plurality of outputs of said Pterm elements;
- at least one PAL array coupled to said at least one PLA array, said at least one PAL array having a plurality of Pterm elements each having an input and an output, and a plurality of AND gates each having an output, and an input coupled to one of said plurality of outputs of said Pterm elements of said PAL array;
- a plurality of PLA ORterms disposed within said Pterm elements of said PAL array, each of said PLA ORterms having an output, and inputs coupled to said outputs of said AND gates of said PLA array, and a plurality of OR gates each having an output, and an input coupled to the output of said PLA ORterms;
- and
- a plurality of OR gates each having an output, and two inputs, one of said inputs for receiving one of the outputs of said AND gates of the PAL array, and the other of said inputs receiving the output of said OR gates of said PLA ORterms, the output of said OR gate feeds a macro cell circuit connected to the condensed single block PLA plus PAL circuit.
An improved condensed single block PLA plus PAL architecture having at least one PLA array having a plurality of Pterm elements each having an input and an output, a plurality of ORterms each having an input and an output, and a plurality of AND gates each having an input coupled to one of said plurality of outputs of said Pterm elements and an output coupled to each of said ORterm elements, and at least one PAL array coupled to said at least one PLA array, said at least one PAL array having a plurality of Pterm elements each having an input and an output, and a plurality of AND gates each having an output, and an input coupled to one of said plurality of outputs of said Pterm elements of said PAL array, the improvement comprising:
- disposing the PLA ORterms within the Pterms of the PAL array such that the PAL array with PLA ORterms is disposed adjacent the PLA array, and the PLA Pterm elements are coupled with the PLA ORterm elements through both said PLA array and said PAL array.
Dependencies are inferred from the claim text.