Chip-sized package having metal circuit substrate
AssigneeSamsung Electronics Co., Ltd.
InventorSang Hyuk Lee
Life of this patent
Estimating the term…
Abstract
A chip-sized semiconductor package having a semiconductor chip formed with bonding pads; a circuit board provided with contact pads for electrically connecting the circuit board to external terminals, and circuit patterns for electrically connecting the circuit board to the chip; a tape bonding the circuit board to the chip; and wires electrically connecting the circuit board to the bonding pads on the chip; the package being encapsulated by a molding compound so that a part of a surface of the circuit board where the contact pads are formed is exposed.
Claims6
A chip-sized semiconductor package, comprising:
- a semiconductor chip having a plurality of bonding pads centrally formed thereon;
- a circuit board having at least one metal layer, at least one electrically non-conductive layer formed on said metal layer, and a plurality of circuit patterns formed on said electrically non-conductive layer, each circuit pattern having a contact pad, said circuit board having an outer perimeter;
- a tape bonding said circuit board to said semiconductor chip;
- a plurality of wires electrically connecting respective ones of said circuit patterns of said circuit board to respective ones of said bonding pads of said semiconductor chip;
- and
- a molding compound encapsulating said semiconductor chip and said plurality of wires;
- said circuit board being stepped adjacent said outer perimeter thereof so as to have an uplifted outer perimetrical bordering surface and a sunk central surface;
- said uplifted outer perimetrical bordering surface having said plurality of contact pads, for being electrically connected to external terminals;
- said sunk central surface having said plurality of circuit patterns, for being electrically connected to said bonding pads of said semiconductor chip;
- and said molding compound partially encapsulating said circuit board, so that said contact pads remain exposed.
The chip-sized semiconductor package, comprising:
- a semiconductor chip having a plurality of bonding pads peripherally formed thereon:
- a circuit board having at least one metal layer, at least one electrically non-conductive layer formed on said metal layer, and a plurality of circuit patterns formed on said electrically non-conductive layer, each circuit pattern having a contact pad, said circuit board having an outer perimeter;
- a tape bonding said circuit board to said semiconductor chip;
- a plurality of wires electrically connecting said circuit patterns of said circuit board to said bonding pads of said semiconductor chip;
- and
- a molding compound encapsulating said semiconductor chip and said plurality of wires;
- said circuit board being stepped adjacent said outer perimeter thereof so as to have an uplifted central surface and a sunk outer perimetrical bordering surface;
- said uplifted central surface having said plurality of contact pads, for being electrically connected to external terminals;
- said sunk outer perimetrical bordering surface having said plurality of circuit patterns, for being electrically connected to said bonding pads of said semiconductor chip;
- and said molding compound partially encapsulating said circuit board so that said contact pads remain exposed.
Dependencies are inferred from the claim text.